公开(公告)号：US5742091A

公开(公告)日：1998-04-21

申请号：US788361

申请日：1997-01-24

Applicant: Francois Hebert

Inventor： Francois Hebert

IPC: H01L23/522 ,  H01L27/08 ,  H01L29/76 ,  H01L29/00

CPC classification number: H01L23/5222 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: A semiconductor device includes at least one passive device and is configured such that parasitic capacitances associated with the passive device are minimized. A substrate layer of the semiconductor device is formed of a substrate material characterized by a first dielectric constant. The substrate layer has at least one deep trench formed therein, and the deep trench is filled with a trench fill material characterized by a second, effective, dielectric constant that is lower than the first dielectric constant. A field layer is formed on a surface of the substrate layer over the deep trench. Finally, the passive device is formed on a surface of the field layer.

Abstract translation: 半导体器件包括至少一个无源器件，并且被配置为使得与无源器件相关联的寄生电容最小化。 半导体器件的衬底层由以第一介电常数为特征的衬底材料形成。 衬底层具有形成在其中的至少一个深沟槽，并且深沟槽填充有沟槽填充材料，其特征在于低于第一介电常数的第二有效介电常数。 在深沟槽上的衬底层的表面上形成场层。 最后，无源器件形成在场层的表面上。

公开(公告)号：US5614758A

公开(公告)日：1997-03-25

申请号：US297634

申请日：1994-08-29

Applicant: Francois Hebert

Inventor： Francois Hebert

IPC: H01L21/331 ,  H01L27/082 ,  H01L29/43

CPC classification number: H01L29/66303 ,  Y10S148/011

Abstract: A self-aligned fully-walled monocrystalline silicon emitter-base structure for a bipolar transistor and methods for producing the structure are provided. The methods involve creating an oxide side wall surrounding a monocrystalline silicon emitter-base structure by first defining the emitter region in a base island region. Successive oxide layers are deposited on top of the emitter region and etched back to produce an oxide wall around the entire perimeter of the emitter region. In a preferred embodiment of the invention a metal silicide is also formed across the top of the base island region of the semiconductor outside of the emitter region. Since the extrinsic base region, outside of the oxide sidewalls, is entirely covered by a low resistance silicide film, the base contact area can be significantly reduced compared to prior art devices.The process results in a fully-walled emitter-base structure made of monocrystalline silicon which exhibits improved high-frequency performance. The peripheral emitter-base capacitance is substantially decreased by the oxide walls which surround the emitter sides. Since the sides of the emitter are walled, no lateral current injection can occur. Bipolar transistors which employ the claimed process exhibit an increased emitter-base breakdown and a reduced forward tunneling current since high sidewall doping levels are eliminated.

Abstract translation: 提供了一种用于双极晶体管的自对准全壁单晶硅发射极 - 基极结构及其制造方法。 该方法包括通过首先限定基岛区域中的发射极区域来形成围绕单晶硅发射极 - 基极结构的氧化物侧壁。 连续的氧化物层沉积在发射极区域的顶部并被回蚀刻以在发射极区域的整个周边周围产生氧化物壁。 在本发明的一个优选实施例中，金属硅化物也形成在发射极区外部的半导体基岛区域的顶部。 由于外部碱性区域在氧化物侧壁外部被低电阻硅化物膜完全覆盖，所以与现有技术的器件相比，基极接触面积可以显着降低。 该过程产生了由单晶硅制成的完全壁的发射极 - 基极结构，其表现出改善的高频性能。 外围发射极 - 基极电容通过围绕发射极侧面的氧化物壁显着减小。 由于发射极的侧壁是壁的，因此不会发生横向电流注入。 采用所要求保护的方法的双极晶体管表现出增加的发射极 - 基极击穿和减少的正向隧穿电流，因为消除了高侧壁掺杂水平。

公开(公告)号：US5411913A

公开(公告)日：1995-05-02

申请号：US236387

申请日：1994-04-29

Applicant: Rashid Bashir ,  Francois Hebert ,  Datong Chen

Inventor： Rashid Bashir ,  Francois Hebert ,  Datong Chen

IPC: H01L21/3105 ,  H01L21/763 ,  H01L21/311 ,  H01L21/76

CPC classification number: H01L21/31056 ,  H01L21/763

Abstract: A device isolation scheme that is particularly suited to the fabrication of high density, high performance CMOS, bipolar, or BiCMOS devices, and overcomes many of the problems associated with existing isolation methods. Photolithographic techniques are used to define active regions on a substrate. Using the photoresist as a mask for the active regions, the silicon in the inactive regions is etched. A pad oxide layer and nitride layer are then formed on the substrate. A layer of oxide is then deposited and photolithographic techniques are again used to define the locations for desired trench structures. After removal of the remaining photoresist, deep trenches are etched in the silicon substrate. An oxidation step is then carried out to provide a layer of oxide lining the trenches, followed by deposition of a layer of poly-silicon over the substrate, filling the trenches. The poly-silicon layer is etched back, removing it from the tops of the trenches and the field regions, and leaving a poly-silicon spacer on the sides of those portions of the previously deposited oxide layer which cover the active regions. The spacers are used to align a photoresist mask which is used to etch away the oxide layer on top of the active regions. The spacers are then removed while keeping the photoresist mask intact, thereby protecting the poly-silicon on top of the trenches. The photoresist mask is then removed and the poly-silicon on top of each trench is oxidized to cap the trench. The result is a highly planar surface in which active regions are separated by field oxide or poly-silicon filled trenches.

Abstract translation: 特别适用于制造高密度，高性能CMOS，双极或BiCMOS器件的器件隔离方案，并克服了与现有隔离方法相关的许多问题。 光刻技术用于定义衬底上的有源区。 使用光致抗蚀剂作为有源区的掩模，蚀刻非活性区中的硅。 然后在衬底上形成焊盘氧化物层和氮化物层。 然后沉积一层氧化物，再次使用光刻技术来定义所需沟槽结构的位置。 在除去剩余的光致抗蚀剂之后，在硅衬底中蚀刻深沟槽。 然后进行氧化步骤以提供在沟槽内衬的氧化层，随后在衬底上沉积多晶硅层，填充沟槽。 将多晶硅层回蚀刻，将其从沟槽和场区域的顶部除去，并且在覆盖活性区域的先前沉积的氧化物层的那些部分的侧面留下多晶硅间隔物。 间隔物用于对准用于蚀刻掉活性区域顶部上的氧化物层的光致抗蚀剂掩模。 然后除去间隔物，同时保持光致抗蚀剂掩模完好无损，从而保护沟槽顶部的多晶硅。 然后去除光致抗蚀剂掩模，并且每个沟槽顶部上的多晶硅被氧化以覆盖沟槽。 结果是高度平坦的表面，其中有源区域被场氧化物或多晶硅填充的沟槽分离。

公开(公告)号：US4654687A

公开(公告)日：1987-03-31

申请号：US717118

申请日：1985-03-28

Applicant: Francois Hebert

Inventor： Francois Hebert

IPC: H01L29/06 ,  H01L29/72 ,  H01L29/08

CPC classification number: H01L29/0692 ,  Y10S148/011 ,  Y10S148/145

Abstract: Structures which improve the high frequency performance of bipolar discrete or integrated transistors through minimization of base contact size and hence collector-base capacitance (and collector-substrate capacitance, if integrated), are disclosed. The transistor comprises at least one elongate emitter arm and substantially minimum-dimension base contacts positioned one facing each side of each emitter arm at at least a minimum dimension from each emitter arm. A base diffusion area is positioned under and is minimum-dimensionally larger than the outer perimeter of the areas bounded by all of the smallest imaginary triangles each including a base contact and a facing emitter arm. Specific examples are described, namely a so-called "lozenge" structure, for relatively narrow emitters, a "cross" structure for wider emitters, and a "T" structure.

Abstract translation: 公开了通过最小化基极接触尺寸和集电极基极电容（以及集电极 - 基板电容，如果集成）来改善双极型分立或集成晶体管的高频性能的结构。 该晶体管包括至少一个细长的发射臂和基本上最小尺寸的基座触点，每个发射臂至少与每个发射臂的最小尺寸相对定向。 基底扩散区域位于由包括底部接触件和面向发射器臂的所有最小假想三角形界限的区域的外周的下方并且小于其尺寸。 对于较窄的发射体，对于较宽的发射体的“交叉”结构和“T”结构来说明具体实例，即所谓的“菱形”结构。

公开(公告)号：US09524957B2

公开(公告)日：2016-12-20

申请号：US13358718

申请日：2012-01-26

Applicant: Francois Hebert ,  Steven R. Rivet ,  Michael Althar ,  Peter Oaklander

Inventor： Francois Hebert ,  Steven R. Rivet ,  Michael Althar ,  Peter Oaklander

IPC: H01R43/00 ,  H01L25/16 ,  H01L23/373 ,  H01L23/433 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L23/64

CPC classification number: H01L25/18 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/367 ,  H01L23/3732 ,  H01L23/4334 ,  H01L23/49517 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/645 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/16 ,  H01L2224/05553 ,  H01L2224/13147 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32145 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/83855 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/06589 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/10162 ,  H01L2924/12032 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/1425 ,  H01L2924/14253 ,  H01L2924/1426 ,  H01L2924/181 ,  Y10T29/49121 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments disclosed herein provide for a circuit including first die having an active side and a backside, wherein the first die is flip-chip mounted to a carrier. The circuit also includes a second die stacked on the backside of the first die, wherein the second die is stacked on the first die such that a backside of the second die is facing the backside of the first die and an active side of the second die faces away from the first die.

Abstract translation: 本文公开的实施例提供了包括具有有源侧和背侧的第一管芯的电路，其中第一管芯被倒装芯片安装到载体上。 电路还包括堆叠在第一管芯的背面上的第二管芯，其中第二管芯堆叠在第一管芯上，使得第二管芯的背面面向第一管芯的背面，第二管芯的有源侧 面对远离第一个模具。

公开(公告)号：US08362555B2

公开(公告)日：2013-01-29

申请号：US12796178

申请日：2010-06-08

Applicant: Dev Alok Girdhar ,  Francois Hebert

Inventor： Dev Alok Girdhar ,  Francois Hebert

IPC: H01L29/66

CPC classification number: H01L27/088

Abstract: A voltage converter includes an output circuit having a high side device and a low side device which can be formed on a single die (i.e. a “PowerDie”) and connected to each other through a semiconductor substrate. Both the high side device and the low side device can include lateral diffused metal oxide semiconductor (LDMOS) transistors. Because both output transistors include the same type of transistors, the two devices can be formed simultaneously, thereby reducing the number of photomasks over other voltage converter designs. The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with, the PowerDie.

Abstract translation: 电压转换器包括具有高侧器件和低侧器件的输出电路，其可以形成在单个管芯（即PowerDie）上，并通过半导体衬底相互连接。 高侧器件和低侧器件都可以包括横向扩散的金属氧化物半导体（LDMOS）晶体管。 因为两个输出晶体管都包含相同类型的晶体管，所以可以同时形成两个器件，从而减少超过其它电压转换器设计的光掩模数量。 电压转换器还可以包括在不同的管芯上的控制器电路，其可以与PowerDie电耦合并与其一体化。

公开(公告)号：US20120293474A1

公开(公告)日：2012-11-22

申请号：US13233667

申请日：2011-09-15

Applicant: I-Shan Sun ,  Francois Hebert ,  Rick Carlton Jerome

Inventor： I-Shan Sun ,  Francois Hebert ,  Rick Carlton Jerome

IPC: G09G5/10 ,  B05D1/36 ,  B05D5/06 ,  G01J1/42 ,  G01J1/02

CPC classification number: G01J1/0488 ,  G01J1/42 ,  G01J1/4204 ,  G09G2360/144

Abstract: Systems and methods for facilitating lift-off processes are provided. In one embodiment, a method for pattering a thin film on a substrate comprises: depositing a first sacrificial layer of photoresist material onto a substrate such that one or more regions of the substrate are exposed through the first sacrificial layer; depositing a protective layer over at least part of the first sacrificial layer; partially removing the first sacrificial layer to form at least one gap between the protective layer and the substrate; depositing an optical coating over the protective layer and the one or more regions of the substrate exposed through the first sacrificial layer, wherein the optical coating deposited over the protective layer is separated by the at least one gap from the optical coating deposited over the regions of the substrate exposed through the first sacrificial layer; and removing the first sacrificial layer.

Abstract translation: 提供了用于促进剥离过程的系统和方法。 在一个实施例中，用于在衬底上图案化薄膜的方法包括：将光致抗蚀剂材料的第一牺牲层沉积到衬底上，使得衬底的一个或多个区域通过第一牺牲层暴露; 在第一牺牲层的至少一部分上沉积保护层; 部分地去除所述第一牺牲层以在所述保护层和所述衬底之间形成至少一个间隙; 在所述保护层上沉积光学涂层，并且通过所述第一牺牲层暴露出所述衬底的所述一个或多个区域，其中沉积在所述保护层上的所述光学涂层被所述光学涂层的所述至少一个间隙与沉积在 所述衬底通过所述第一牺牲层暴露; 以及去除所述第一牺牲层。

公开(公告)号：US20110260174A1

公开(公告)日：2011-10-27

申请号：US12950202

申请日：2010-11-19

Applicant: Francois Hebert

Inventor： Francois Hebert

IPC: H01L29/778 ,  H01L21/335 ,  H01L29/12

CPC classification number: H01L27/0255 ,  H01L21/8258 ,  H01L27/0629 ,  H01L27/0688 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/8611 ,  H01L29/872

Abstract: Exemplary embodiments provide structures and methods for power devices with integrated clamp structures. The integration of clamp structures can protect the power device, e.g., from electrical overstress (EOS). In one embodiment, active devices can be formed over a substrate, while a clamp structure can be integrated outside the active regions of the power device, for example, under the active regions and/or inside the substrate. Integrating clamp structure outside active regions of power devices can maximize the active area for a given die size and improve robustness of the clamped device since the current will spread in the substrate by this integration.

Abstract translation: 示例性实施例提供了具有集成钳位结构的功率器件的结构和方法。 夹紧结构的集成可以保护功率器件，例如不受电力过应力（EOS）的影响。 在一个实施例中，有源器件可以形成在衬底上，而钳位结构可以集成在功率器件的有源区域外部，例如在有源区域下方和/或衬底内部。 在功率器件的有源区域之外集成钳位结构可以使给定管芯尺寸的有效面积最大化，并且改善钳位器件的鲁棒性，因为电流将通过该积分在衬底中扩展。

公开(公告)号：US20110180806A1

公开(公告)日：2011-07-28

申请号：US12946669

申请日：2010-11-15

Applicant: Francois Hebert

Inventor： Francois Hebert

IPC: H01L29/20 ,  H01L21/20

CPC classification number: H01L29/7787 ,  H01L21/0242 ,  H01L21/0245 ,  H01L21/0254 ,  H01L21/02658 ,  H01L21/76281 ,  H01L21/8258 ,  H01L27/085 ,  H01L29/2003 ,  H01L29/66462

Abstract: A structure and method for a semiconductor device includes a silicon device layer and a gallium nitride (GaN) device layer. In an embodiment, the silicon device layer and the GaN device layer have upper surfaces which are coplanar with each other. In another embodiment, the GaN device layer does not directly underlie the silicon device layer, and the silicon device layer does not directly underlie the GaN device layer. The semiconductor device can further include a silicon-based semiconductor device formed on and/or within the silicon device layer, and a nitride-based semiconductor device formed on and/or within the GaN device layer. The GaN device layer can include a plurality of layers which can be formed as conformal blanket layers and then planarized, or which can be selectively formed then planarized.

Abstract translation: 半导体器件的结构和方法包括硅器件层和氮化镓（GaN）器件层。 在一个实施例中，硅器件层和GaN器件层具有彼此共面的上表面。 在另一个实施例中，GaN器件层不直接位于硅器件层之下，并且硅器件层不直接位于GaN器件层的下面。 半导体器件还可以包括形成在硅器件层上和/或内部的硅基半导体器件，以及形成在GaN器件层上和/或内部的氮化物基半导体器件。 GaN器件层可以包括可以形成为保形覆盖层然后平坦化的多个层，或者可以选择性地形成，然后进行平面化。

公开(公告)号：US20110156679A1

公开(公告)日：2011-06-30

申请号：US12938589

申请日：2010-11-03

Applicant: Dev Alok Girdhar ,  Francois Hebert

Inventor： Dev Alok Girdhar ,  Francois Hebert

IPC: H01L27/06 ,  H01L21/336 ,  G05F1/618

CPC classification number: H01L27/0629 ,  H01L27/088 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/7834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and structure for a voltage converter including a trench field effect transistor (FET) and a trench guarded Schottky diode which is integrated with the trench FET. In an embodiment, a voltage converter can include a lateral FET, a trench FET, and a trench guarded Schottky diode integrated with the trench FET. A method to form a voltage converter can include the formation of a trench FET gate, a trench guarded Schottky diode gate, and a lateral FET gate using a single conductive layer such as a polysilicon layer.

Abstract translation: 一种电压转换器的方法和结构，包括与沟槽FET集成的沟槽场效应晶体管（FET）和沟槽保护肖特基二极管。 在一个实施例中，电压转换器可以包括横向FET，沟槽FET和与沟槽FET集成的沟槽保护肖特基二极管。 形成电压转换器的方法可以包括使用诸如多晶硅层的单个导电层形成沟槽FET栅极，沟槽保护肖特基二极管栅极和横向FET栅极。