公开(公告)号：US20080173958A1

公开(公告)日：2008-07-24

申请号：US11625573

申请日：2007-01-22

申请人： Haoren Zhuang ,  Matthias Lipinski ,  Jingyu Lian ,  Chandrasekhar Sarma

发明人： Haoren Zhuang ,  Matthias Lipinski ,  Jingyu Lian ,  Chandrasekhar Sarma

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/4916 ,  H01L21/28035 ,  H01L29/78

摘要： Various illustrative embodiments of methods for manufacturing a semiconductor device are described. These methods may include, for example, forming a first polysilicon layer above a substrate, wherein the first polysilicon layer comprises a doped portion, and forming a second polysilicon layer over a surface of the first polysilicon layer. Also, various illustrative embodiments of semiconductor devices are described that may be manufactured such as by the various methods described herein.

摘要翻译： 描述用于制造半导体器件的方法的各种说明性实施例。 这些方法可以包括例如在衬底上形成第一多晶硅层，其中第一多晶硅层包括掺杂部分，并且在第一多晶硅层的表面上形成第二多晶硅层。 而且，描述了半导体器件的各种说明性实施例，其可以通过本文所述的各种方法来制造。

公开(公告)号：US20070190795A1

公开(公告)日：2007-08-16

申请号：US11352565

申请日：2006-02-13

申请人： Haoren Zhuang ,  Jiang Yan ,  Jin-Ping Han ,  Jingyu Lian ,  Alois Gutmann

发明人： Haoren Zhuang ,  Jiang Yan ,  Jin-Ping Han ,  Jingyu Lian ,  Alois Gutmann

IPC分类号： H01L21/302

CPC分类号： H01L21/0206 ,  H01L21/28123 ,  H01L29/513 ,  H01L29/517

摘要： Method for fabricating semiconductor devices with high-K materials without the presence of undesired formations of the high-K material. A preferred embodiment comprises forming a layer of material over a layer of a high-K material, etching the layer of material to expose a portion of the high-K material, performing a CDE (Chemical Downstream Etch) to remove any residual material formed during the etching, and etching the layer of the high-K material into alignment with remaining portions of the layer of material. The removal of the residual material results in a predictable trimming of the high-K material so that the semiconductor device has predictable and consistent performance, which is not possible if the high-K material has unpredictable dimensions.

摘要翻译： 用于制造具有高K材料的半导体器件的方法，而不存在不需要的高K材料的形成。 优选的实施方案包括在高K材料层上形成一层材料，蚀刻该材料层以暴露一部分高K材料，进行CDE（化学下游蚀刻）去除在 蚀刻和蚀刻高K材料层与材料层的剩余部分对准。 剩余材料的去除导致高K材料的可预测的修整，使得半导体器件具有可预测和一致的性能，如果高K材料具有不可预测的尺寸，则这是不可能的。

公开(公告)号：US09070759B2

公开(公告)日：2015-06-30

申请号：US11526499

申请日：2006-09-25

申请人： Jin-Ping Han ,  Haoren Zhuang ,  Jiang Yan ,  Jingyu Lian ,  Manfred Eller

发明人： Jin-Ping Han ,  Haoren Zhuang ,  Jiang Yan ,  Jingyu Lian ,  Manfred Eller

IPC分类号： H01L21/336 ,  H01L21/311 ,  H01L29/51 ,  H01L29/78 ,  H01L29/423 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8238

CPC分类号： H01L29/4983 ,  H01L21/28017 ,  H01L21/28123 ,  H01L21/28194 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/82385 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78

摘要： A method of making a semiconductor device is disclosed. A device is fabricated on a semiconductor body. A gate electrode is disposed over the semiconductor body with a gate dielectric between the gate electrode and the semiconductor body, wherein the gate dielectric has a length greater than the gate electrode. A first source/drain region is disposed within the semiconductor body adjacent to the first edge of the gate with the gate dielectric at least partially overlapping the first source/drain region, and a second source/drain region is disposed within the semiconductor body adjacent to the first edge of the gate with the gate dielectric at least partially overlapping the second source/drain region.

摘要翻译： 公开了制造半导体器件的方法。 器件制造在半导体主体上。 栅电极设置在半导体本体上，在栅电极和半导体本体之间具有栅极电介质，其中栅极电介质具有大于栅电极的长度。 第一源极/漏极区域设置在与栅极的第一边缘相邻的半导体本体内，栅极电介质至少部分地与第一源极/漏极区域重叠，并且第二源极/漏极区域设置在与半导体本体相邻的第二源极/漏极区域内 具有栅极电介质的栅极的第一边缘至少部分地与第二源极/漏极区重叠。

公开(公告)号：US20080076214A1

公开(公告)日：2008-03-27

申请号：US11526499

申请日：2006-09-25

申请人： Jin-Ping Han ,  Haoren Zhuang ,  Jiang Yan ,  Jingyu Lian ,  Manfred Eller

发明人： Jin-Ping Han ,  Haoren Zhuang ,  Jiang Yan ,  Jingyu Lian ,  Manfred Eller

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L29/4983 ,  H01L21/28017 ,  H01L21/28123 ,  H01L21/28194 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/82385 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78

摘要： A method of making a semiconductor device is disclosed. A device is fabricated on a semiconductor body. A gate electrode is disposed over the semiconductor body with a gate dielectric between the gate electrode and the semiconductor body, wherein the gate dielectric has a length greater than the gate electrode. A first source/drain region is disposed within the semiconductor body adjacent to the first edge of the gate with the gate dielectric at least partially overlapping the first source/drain region, and a second source/drain region is disposed within the semiconductor body adjacent to the first edge of the gate with the gate dielectric at least partially overlapping the second source/drain region.

摘要翻译： 公开了制造半导体器件的方法。 器件制造在半导体主体上。 栅电极设置在半导体本体上，在栅电极和半导体本体之间具有栅极电介质，其中栅极电介质具有大于栅电极的长度。 第一源极/漏极区域设置在与栅极的第一边缘相邻的半导体本体内，栅极电介质至少部分地与第一源极/漏极区域重叠，并且第二源极/漏极区域设置在与半导体本体相邻的第二源极/漏极区域内 具有栅极电介质的栅极的第一边缘至少部分地与第二源极/漏极区重叠。

公开(公告)号：US07042705B2

公开(公告)日：2006-05-09

申请号：US10356690

申请日：2003-01-30

申请人： Haoren Zhuang ,  Ulrich Egger ,  Kazuhiro Tomioka ,  Jingyu Lian ,  Nicolas Nagel ,  Andreas Hilliger ,  Gerhard Beitel

发明人： Haoren Zhuang ,  Ulrich Egger ,  Kazuhiro Tomioka ,  Jingyu Lian ,  Nicolas Nagel ,  Andreas Hilliger ,  Gerhard Beitel

IPC分类号： H01G4/10

CPC分类号： H01L28/55 ,  H01L21/31116 ,  H01L28/57

摘要： The present invention provides a sidewall oxygen diffusion barrier and a method for fabricating the sidewall oxygen diffusion barrier that reduces the diffusion of oxygen into contact plugs during a CW hole reactive ion etch of a ferroelectric capacitor of an FeRAM device. In one embodiment the sidewall barrier is formed from a substrate fence. In another embodiment, the sidewall barrier is formed by etching back an oxygen barrier.

摘要翻译： 本发明提供一种侧壁氧扩散阻挡层和制造侧壁氧扩散阻挡层的方法，该方法在FeRAM器件的铁电电容器的CW孔反应离子蚀刻期间减少氧气扩散到接触塞中。 在一个实施例中，侧壁屏障由衬底围栏形成。 在另一个实施例中，通过蚀刻回氧屏障来形成侧壁屏障。

公开(公告)号：US07001780B2

公开(公告)日：2006-02-21

申请号：US10635140

申请日：2003-08-06

申请人： Haoren Zhuang ,  Ulrich Egger ,  Jingyu Lian ,  Stefan Gernhardt ,  Hiroyuki Kanaya

发明人： Haoren Zhuang ,  Ulrich Egger ,  Jingyu Lian ,  Stefan Gernhardt ,  Hiroyuki Kanaya

IPC分类号： H01L21/00

CPC分类号： H01L28/86 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65 ,  H01L28/90

摘要： A ferroelectric device includes a bottom electrode on which are formed ferrocapacitor elements and, over the ferroelectric elements, top electrodes. The bottom electrodes are connected to lower layers of the device via conductive plugs, and the plugs and bottom electrodes are spaced apart by barrier elements of Ir and/or IrO2. The barrier elements are narrower than the bottom electrode elements, and are formed by a separate etching process. This means that Ir fences are not formed during the etching of the bottom electrode. Also, little Ir and/or IrO2 diffuses through the bottom electrode to the ferroelectric elements, and therefore there is little risk of damage to the ferroelectric material.

摘要翻译： 铁电体元件包括底电极，其上形成有铁电体元件，并且在铁电元件上形成顶电极。 底部电极通过导电插头连接到器件的下层，并且插头和底部电极被Ir和/或IrO 2的阻挡元件隔开。 阻挡元件比底部电极元件窄，并且通过单独的蚀刻工艺形成。 这意味着在底电极的蚀刻期间不形成Ir栅栏。 此外，很少的Ir和/或IrO 2 <2>通过底部电极扩散到铁电体元件，因此几乎不会损坏铁电体材料的风险。

公开(公告)号：US06897501B2

公开(公告)日：2005-05-24

申请号：US10248897

申请日：2003-02-28

申请人： Haoren Zhuang ,  Ulrich Egger ,  Jingyu Lian ,  Gerhard Beitel ,  Karl Hornik

发明人： Haoren Zhuang ,  Ulrich Egger ,  Jingyu Lian ,  Gerhard Beitel ,  Karl Hornik

IPC分类号： H01L21/02 ,  H01L21/8246 ,  H01L27/08 ,  H01L27/115 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/11502 ,  H01L27/0805 ,  H01L27/11507 ,  H01L28/55

摘要： A capacitor structure having a capacitor with a top electrode, a bottom electrode, and a capacitor dielectric layer between the top and bottom electrodes is disclosed. The capacitor includes upper and lower portions. The demarcation between the upper and lower portion is located between top and bottom surfaces of the capacitor dielectric layer. A dielectric layer is provided on the sidewalls of the upper portion of the capacitor to prevent shorting between the electrodes that can be caused by a conductive fence formed during processing.

摘要翻译： 公开了一种电容器结构，其具有在顶部电极和底部电极之间具有顶部电极，底部电极和电容器电介质层的电容器。 电容器包括上部和下部。 上部和下部之间的分界位于电容器介电层的顶表面和底表面之间。 在电容器的上部的侧壁上设置有电介质层，以防止在加工过程中形成的导电栅栏引起的电极之间的短路。

公开(公告)号：US20050029563A1

公开(公告)日：2005-02-10

申请号：US10635140

申请日：2003-08-06

申请人： Haoren Zhuang ,  Ulrich Egger ,  Jingyu Lian ,  Stefan Gernhardt ,  Hiroyuki Kanaya

发明人： Haoren Zhuang ,  Ulrich Egger ,  Jingyu Lian ,  Stefan Gernhardt ,  Hiroyuki Kanaya

IPC分类号： H01L21/02 ,  H01L21/8246 ,  H01L31/119

CPC分类号： H01L28/86 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65 ,  H01L28/90

摘要： A ferroelectric device includes a bottom electrode on which are formed ferrocapacitor elements and, over the ferroelectric elements, top electrodes. The bottom electrodes are connected to lower layers of the device via conductive plugs, and the plugs and bottom electrodes are spaced apart by barrier elements of Ir and/or IrO2. The barrier elements are narrower than the bottom electrode elements, and are formed by a separate etching process. This means that Ir fences are not formed during the etching of the bottom electrode. Also, little Ir and/or IrO2 diffuses through the bottom electrode to the ferroelectric elements, and therefore there is little risk of damage to the ferroelectric material.

摘要翻译： 铁电体元件包括底电极，其上形成有铁电体元件，并且在铁电元件上形成顶电极。 底部电极通过导电插头连接到器件的下层，并且插头和底部电极被Ir和/或IrO 2的屏障元件隔开。 阻挡元件比底部电极元件窄，并且通过单独的蚀刻工艺形成。 这意味着在底电极的蚀刻期间不形成Ir栅栏。 另外，少量Ir和/或IrO 2通过底部电极扩散到铁电体元件，因此几乎不会损坏铁电体材料。

公开(公告)号：US08138055B2

公开(公告)日：2012-03-20

申请号：US12850119

申请日：2010-08-04

申请人： Jin-Ping Han ,  Alois Gutmann ,  Roman Knoefler ,  Jiang Yan ,  Chris Stapelmann ,  Jingyu Lian ,  Yung Fu Chong

发明人： Jin-Ping Han ,  Alois Gutmann ,  Roman Knoefler ,  Jiang Yan ,  Chris Stapelmann ,  Jingyu Lian ,  Yung Fu Chong

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask.

摘要翻译： 在制造半导体器件的方法中，在包括第一栅极电极材料的pFET区域的衬底上形成第一栅极堆叠。 在pFET区域蚀刻衬底的源/漏区，并且在pFET区域蚀刻第一栅极堆叠的第一栅电极材料。 蚀刻对蚀刻氧化物和/或氮化物材料至少部分选择性，使得nFET区域被氮化物层（和/或第一氧化物层）屏蔽，并且使得pFET区域的间隔结构至少部分保留。 形成源极/漏极凹部，并且通过蚀刻去除第一栅电极材料的至少一部分，以在pFET区域形成栅电极凹部。 SiGe材料在源极/漏极凹槽中以及在pFET区域的栅极电极凹槽中外延生长。 SMT效应由相同的氮化物nFET掩模实现。

公开(公告)号：US20080119019A1

公开(公告)日：2008-05-22

申请号：US11602117

申请日：2006-11-20

申请人： Jin-Ping Han ,  Alois Gutmann ,  Roman Knoefler ,  Jiang Yan ,  Chris Stapelmann ,  Jingyu Lian ,  Yung Fu Chong

发明人： Jin-Ping Han ,  Alois Gutmann ,  Roman Knoefler ,  Jiang Yan ,  Chris Stapelmann ,  Jingyu Lian ,  Yung Fu Chong

IPC分类号： H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask.

摘要翻译： 在制造半导体器件的方法中，在包括第一栅极电极材料的pFET区域的衬底上形成第一栅极堆叠。 在pFET区域蚀刻衬底的源/漏区，并且在pFET区域蚀刻第一栅极堆叠的第一栅电极材料。 蚀刻对蚀刻氧化物和/或氮化物材料至少部分选择性，使得nFET区域被氮化物层（和/或第一氧化物层）屏蔽，并且使得pFET区域的间隔结构至少部分保留。 形成源极/漏极凹部，并且通过蚀刻去除第一栅电极材料的至少一部分，以在pFET区域形成栅电极凹部。 SiGe材料在源极/漏极凹槽中以及在pFET区域的栅极电极凹槽中外延生长。 SMT效应由相同的氮化物nFET掩模实现。