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    Manufacturing method of semiconductor device
    22.
    发明申请
    Manufacturing method of semiconductor device 有权
    半导体器件的制造方法

    公开(公告)号：US20050106843A1

    公开(公告)日：2005-05-19

    申请号：US10952381

    申请日：2004-09-29

    申请人： Hirotoshi Kubo ,  Yasuhiro Igarashi ,  Masahiro Shibuya

    发明人： Hirotoshi Kubo ,  Yasuhiro Igarashi ,  Masahiro Shibuya

    IPC分类号： H01L21/28 ,  H01L21/00 ,  H01L21/04 ,  H01L21/335 ,  H01L21/336 ,  H01L21/82 ,  H01L27/02 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/72 ,  H01L29/772 ,  H01L29/78

    CPC分类号： H01L29/7813 ,  H01L29/456

    摘要： When Ti as a barrier metal layer is brought into contact with a diffusion region of boron provided on a surface of a silicon substrate, there is a problem that boron is absorbed by titanium silicide, and contact resistance is increased. Although there is a method of additionally implanting boron whose amount is equal to the amount of boron absorbed by titanium silicide, there has been a problem that when boron is additionally implanted into, for example, a source region in a p-channel type, the additionally added boron is diffused deeply at the diffusion step, and characteristics are deteriorated. According to the invention, after formation of an element region, boron is additionally implanted into the whole surface at a dosage of about 10% of an element region, and is activated in the vicinity of a surface of a silicon substrate by an alloying process of a barrier metal layer. By this, a specified concentration profile of the element region is kept, and the impurity concentration only in the vicinity of the surface can be raised. Accordingly, even if boron is absorbed by titanium silicide, a specified boron concentration can be kept in the element region, and the increase of contact resistance can be suppressed.

    摘要翻译： 当作为阻挡金属层的Ti与设置在硅衬底的表面上的硼的扩散区域接触时，存在硼被硅化钛吸收的问题，并且接触电阻增加。 虽然存在另外注入硼量的方法，其量等于由硅化钛吸收的硼的量，但是存在如下问题：当将硼另外注入例如p沟道型的源极区时， 在扩散步骤中另外添加硼深度扩散，特性劣化。 根据本发明，在形成元件区域之后，以元素区域的约10％的剂量将硼额外地注入整个表面，并且通过合金化工艺在硅衬底的表面附近活化 阻挡金属层。 由此，保持元件区域的规定的浓度分布，仅能够提高表面附近的杂质浓度。 因此，即使硼被硅化钛吸收，也可以在元件区域中保持规定的硼浓度，能够抑制接触电阻的增加。

    Method for manufacturing semiconductor device
    24.
    发明授权
    Method for manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US07439137B2

    公开(公告)日：2008-10-21

    申请号：US11123248

    申请日：2005-05-06

    申请人： Hiroyasu Ishida ,  Hirotoshi Kubo ,  Shouji Miyahara ,  Masato Onda

    发明人： Hiroyasu Ishida ,  Hirotoshi Kubo ,  Shouji Miyahara ,  Masato Onda

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7813 ,  H01L21/3003 ,  H01L21/76886 ,  H01L21/823487 ,  H01L29/456

    摘要： In a MOSFET, after an element region is formed, a wiring layer is formed subsequently to a barrier metal layer, and hydrogen annealing is performed. However, in the case of an n-channel MOSFET, a threshold voltage is lowered due to an occlusion characteristic of the barrier metal layer. Thus, an increased impurity concentration in a channel layer causes a problem that reduction in an on-resistance is inhibited. According to the present invention, after a barrier metal layer is formed, an opening is provided in the barrier metal layer on an interlayer insulating film, and hydrogen annealing treatment is performed after a wiring layer is formed. Thus, an amount of hydrogen which reaches a substrate is further increased, and lowering of a threshold voltage is suppressed. Moreover, since an impurity concentration in a channel layer can be lowered, an on-resistance is reduced.

    摘要翻译： 在MOSFET中，在形成元件区之后，在阻挡金属层的后面形成布线层，进行氢退火。 然而，在n沟道MOSFET的情况下，由于阻挡金属层的遮挡特性，阈值电压降低。 因此，通道层中杂质浓度的增加引起导通电阻的降低被抑制的问题。 根据本发明，在形成阻挡金属层之后，在层间绝缘膜上的阻挡金属层中设置开口，在形成布线层之后进行氢退火处理。 因此，到达基板的氢的量进一步增加，并且抑制了阈值电压的降低。 此外，由于可以降低沟道层中的杂质浓度，所以导通电阻降低。

    Semiconductor device and manufacturing method thereof
    25.
    发明授权
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US06818492B2

    公开(公告)日：2004-11-16

    申请号：US10016142

    申请日：2001-12-17

    申请人： Hirotoshi Kubo ,  Shigeyuki Murai ,  Hisaaki Tominaga ,  Hidetaka Sawame

    发明人： Hirotoshi Kubo ,  Shigeyuki Murai ,  Hisaaki Tominaga ,  Hidetaka Sawame

    IPC分类号： H01L218238

    CPC分类号： H01L29/66287 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/732

    摘要： This invention provides a semiconductor device which is excellent in high-frequency characteristics, wherein emitter diffusion is performed by a trench formed in a base region, the base resistance is further reduced, and the base-emitter capacitance is also reduced. A base electrode layer makes a contact with the whole surface of the base region. A tapered trench is provided in the base region. A finer emitter region is formed by emitter diffusion from the bottom portion of the trench. Since the base electrode is formed adjacently to the trench, the distance between an active region of the base and the base electrode layer can be shortened and a larger grounded area of a base can also be obtained, therefore the base resistance can be substantially reduced. In addition, by forming a fine region, the base-emitter capacitance between the base and emitter can also be reduced, therefore a transistor excellent in high-frequency characteristics can be obtained.

    摘要翻译： 本发明提供一种高频特性优异的半导体器件，其中通过形成在基极区域中的沟槽进行发射极扩散，基极电阻进一步降低，并且基极 - 发射极电容也降低。 基极层与基极区域的整个表面接触。 在基部区域中设置有锥形沟槽。 通过从沟槽的底部的发射体扩散形成更细的发射极区域。 由于基极与沟槽相邻形成，所以可以缩短基极的有源区域与基极层之间的距离，并且还可以获得更大的基极接地面积，因此能够大幅降低基极电阻。 此外，通过形成微细的区域，也可以减小基极和发射极之间的基极 - 发射极电容，因此可以获得高频特性优异的晶体管。

    Method of manufacturing insulating-gate semiconductor device
    26.
    发明授权
    Method of manufacturing insulating-gate semiconductor device 失效
    绝缘栅半导体器件的制造方法

    公开(公告)号：US06429078B2

    公开(公告)日：2002-08-06

    申请号：US09817118

    申请日：2001-03-27

    申请人： Hirotoshi Kubo

    发明人： Hirotoshi Kubo

    IPC分类号： H01L21336

    CPC分类号： H01L21/763

    摘要： The cell density of power MOSFET used as a switch is determined by the width of the trench formed in the device, the processing limit of which is limited by the spatial resolution of the exposure apparatus used in the photolithographic process. This invention provides a method of manufacturing such devices which overcomes the processing limitation imposed by the exposure apparatus, and doubles the cell density and reduces the input capacitance for further reducing the on-state resistance and improving the switching speed. By forming a second CVD oxide film over a first oxide film defining the opening for forming a trench and subsequent anisotropic RIE etching of the second film, a side-wall film is added to the mask pattern, which promotes a further reduction of the width of the trench by more than one half.

    摘要翻译： 用作开关的功率MOSFET的单元密度由器件中形成的沟槽的宽度确定，其处理限制受光刻工艺中使用的曝光设备的空间分辨率的限制。 本发明提供一种制造这种器件的方法，其克服了曝光设备施加的处理限制，并且使单元密度增加一倍并降低输入电容，从而进一步降低导通电阻并提高切换速度。 通过在限定用于形成沟槽的开口的第一氧化物膜上形成第二CVD氧化膜，随后对第二膜进行各向异性RIE蚀刻，将侧壁膜加入到掩模图案中，这促进了宽度的进一步降低 沟通了一半以上。

    Variable mechanism for mounting angle housed gyro-sensor and method of mounting variable mechanism for mounting angle
    27.
    发明授权
    Variable mechanism for mounting angle housed gyro-sensor and method of mounting variable mechanism for mounting angle 有权
    用于安装角度的陀螺仪传感器的可变机构和安装角度的可变机构的安装方法

    公开(公告)号：US06301982B1

    公开(公告)日：2001-10-16

    申请号：US09380508

    申请日：1999-09-03

    申请人： Hirotoshi Kubo ,  Kazunari Yamakado ,  Yasushi Takahashi ,  Hiroaki Sugino

    发明人： Hirotoshi Kubo ,  Kazunari Yamakado ,  Yasushi Takahashi ,  Hiroaki Sugino

    IPC分类号： G01C1902

    CPC分类号： G01C21/26 ,  G01C19/00 ,  G01C21/16 ,  Y10T74/1218 ,  Y10T74/1232 ,  Y10T74/1243 ,  Y10T74/1257 ,  Y10T74/1289

    摘要： A housed gyro-sensor 31 is housed in a rotation plate 33. The gyro-sensor 31 is mounted so that a rotation operation is enabled in a pitch axis direction about an axis in a mounting hole 24 formed on a housing of an inner face of the car navigation system 21. In this way, as shown in FIG. 8, even when the main body of the car navigation system 21 is not housed horizontally with respect to the vehicle, it is possible to regulate the mounting angle of the housed gyro sensor 31 in a horizontal direction by rotating the rotation plate 33. In order to realize how many times the rotation plate 33 needs to be rotated, standards for angle settings may be provided by directly printing the name of the vehicle type on an outer face of the rotation plate 33 or by printing the major angles.

    摘要翻译： 容纳的陀螺仪传感器31容纳在旋转板33中。陀螺传感器31被安装成使得能够在俯仰轴线方向上围绕形成在内表面的壳体的安装孔24中的轴线的旋转操作 汽车导航系统21。 如图8所示，即使当汽车导航系统21的主体不相对于车辆水平地容纳时，也可以通过旋转旋转板33来调节收纳的陀螺仪传感器31在水平方向上的安装角度。按顺序 为了实现旋转板33需要旋转多少次，可以通过在旋转板33的外表面上直接打印车辆名称或通过打印主角来提供角度设置的标准。

    Semiconductor device with vertical transistors
    29.
    发明授权
    Semiconductor device with vertical transistors 有权
    具有垂直晶体管的半导体器件

    公开(公告)号：US06828626B2

    公开(公告)日：2004-12-07

    申请号：US10253901

    申请日：2002-09-25

    申请人： Makoto Oikawa ,  Hiroki Etou ,  Hirotoshi Kubo ,  Shouji Miyahara

    发明人： Makoto Oikawa ,  Hiroki Etou ,  Hirotoshi Kubo ,  Shouji Miyahara

    IPC分类号： H01L2978

    CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

    摘要： In a conventional power MOSFET, an electric field concentration occurs at a gate electrode bottom portion on the outermost periphery of an operating area, thereby causing a deterioration in high voltage strength between the drain and the source, or between the collector and emitter. In this invention, a trench at the outermost periphery of an operating area is shallower than trenches of the operating area. Thereby, the electric field concentration at the gate electrode bottom portion on the outermost periphery of the operating area is relieved, and a deterioration in high voltage strength between the drain and source is suppressed. Furthermore, by narrowing the outermost peripheral trench aperture portion, trenches different in depth can be formed by an identical step.

    摘要翻译： 在常规功率MOSFET中，在操作区域的最外周的栅电极底部产生电场浓度，从而导致漏极与源极之间或集电极与发射极之间的高电压强度的劣化。 在本发明中，操作区域的最外周的沟槽比操作区域的沟槽浅。 由此，减轻了操作区域的最外周的栅电极底部的电场浓度，并且抑制了漏极与源极之间的高电压强度的劣化。 此外，通过使最外周沟槽开口部分变窄，可以通过相同的步骤形成深度不同的沟槽。

    Insulated gate field effect semiconductor device
    30.
    发明授权
    Insulated gate field effect semiconductor device 有权

    公开(公告)号：US06576955B2

    公开(公告)日：2003-06-10

    申请号：US09917239

    申请日：2001-07-30

    申请人： Hirotoshi Kubo

    发明人： Hirotoshi Kubo

    IPC分类号： H01L2976

    CPC分类号： H01L29/7813 ,  H01L29/4232 ,  H01L29/4238

    摘要： The present invention is intended to form the adjacent trenches by bending them to make a widened portion and a narrowed portion on the substrate of the semiconductor inside the trenches shaped in stripes and to arrange the adjacent widened portions and the narrowed portions alternately to lay the body contact region in the widened portion. By this arrangement, the stability of the potential is improved and thus leakage current is decreased. Further, the on-state resistance can be decreased and an advantage in rule is achieved while improving the channel width per unit area.