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    Semiconductor memory device and self-refresh method therefor
    21.
    发明授权
    Semiconductor memory device and self-refresh method therefor 有权
    半导体存储器件及其自刷新方法

    公开(公告)号：US07573772B2

    公开(公告)日：2009-08-11

    申请号：US11612866

    申请日：2006-12-19

    Applicant: Kyung-Woo Nam ,  Ho-Cheol Lee

    Inventor： Kyung-Woo Nam ,  Ho-Cheol Lee

    IPC: G11C7/00

    CPC classification number: G11C11/406 ,  G11C7/1075 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/40618

    Abstract: A semiconductor memory device and a self-refresh method in which the semiconductor memory device includes a plurality of input/output ports having respective independent operation, a period of self-refresh through one of the plurality of input/output ports being subordinate to a kind of operation through another input/output port. Whereby, a refresh characteristic in a multi-port semiconductor memory device including a dual-port semiconductor memory device may be improved.

    Abstract translation: 一种半导体存储器件和自刷新方法，其中所述半导体存储器件包括具有各自独立操作的多个输入/输出端口，所述多个输入/输出端口中的一个输入/输出端口中的一个从属于一种类型的自刷新周期 的操作通过另一个输入/输出端口。 因此，可以提高包括双端口半导体存储器件的多端口半导体存储器件中的刷新特性。

    Semiconductor package having multiple embedded chips
    23.
    发明申请
    Semiconductor package having multiple embedded chips 有权
    具有多个嵌入式芯片的半导体封装

    公开(公告)号：US20050001300A1

    公开(公告)日：2005-01-06

    申请号：US10803043

    申请日：2004-03-18

    Applicant: Ho-Cheol Lee

    Inventor： Ho-Cheol Lee

    IPC: H01L23/12 ,  H01L25/065 ,  H01L21/48 ,  H01L23/52

    CPC classification number: H01L25/065 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2924/00014

    Abstract: A semiconductor package includes multiple embedded chips, each chip including a common circuit having substantially the same common function. The common circuit in a selected one of the chips is enabled. The common circuit in one or more other ones of the chips is disabled. As a result, the enabled common circuit performs the common function for the selected chip and the one or more other chips.

    Abstract translation: 半导体封装包括多个嵌入式芯片，每个芯片包括具有基本上相同的共同功能的公共电路。 所选择的一个芯片中的公共电路被使能。 一个或多个其他芯片中的公共电路被禁用。 结果，使能的公共电路执行所选择的芯片和一个或多个其他芯片的共同功能。

    Semiconductor memory device with shared data input/output line
    24.
    发明授权
    Semiconductor memory device with shared data input/output line 失效
    具有共享数据输入/输出线的半导体存储器件

    公开(公告)号：US5886947A

    公开(公告)日：1999-03-23

    申请号：US947280

    申请日：1997-10-08

    Applicant: Ho-Cheol Lee

    Inventor： Ho-Cheol Lee

    IPC: G11C11/417 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C11/409 ,  G11C11/413 ,  G11C8/00

    CPC classification number: G11C7/22 ,  G11C7/1048

    Abstract: The semiconductor memory device includes a clock signal generating circuit, a precharge circuit, a write circuit, and an input/output circuit. The clock signal generating circuit generates a second clock signal having a second state of a constant interval irrespective of a period of a first clock signal. The precharge circuit precharges a data input/output line in response to a precharge signal. The write circuit transfers, during a write operation, input data signal to the data input/output line each time the second clock signal is a first state under the state that a power signal and the precharge signal are the first state. The input/output circuit transfers data transmitted to the data input/output line to a cell.

    Abstract translation: 半导体存储器件包括时钟信号发生电路，预充电电路，写入电路和输入/输出电路。 时钟信号发生电路产生具有恒定间隔的第二状态的第二时钟信号，而与第一时钟信号的周期无关。 预充电电路响应于预充电信号对数据输入/输出线进行预充电。 在电源信号和预充电信号为第一状态的状态下，每当第二时钟信号为第一状态时，写入电路在写入操作期间将输入数据信号传送到数据输入/输出线。 输入/输出电路将发送到数据输入/输出线的数据传送到一个单元。

    Semiconductor memory device having high speed parallel transmission line operation and a method for forming parallel transmission lines
    25.
    发明授权
    Semiconductor memory device having high speed parallel transmission line operation and a method for forming parallel transmission lines 失效
    具有高速并行传输线操作的半导体存储器件和用于形成并行传输线的方法

    公开(公告)号：US5663913A

    公开(公告)日：1997-09-02

    申请号：US638373

    申请日：1996-04-26

    Applicant: Ho-Cheol Lee ,  Hyun-Soon Jang

    Inventor： Ho-Cheol Lee ,  Hyun-Soon Jang

    IPC: G11C11/41 ,  G11C7/22 ,  G11C11/407 ,  G11C11/409 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

    CPC classification number: G11C7/22

    Abstract: A semiconductor memory device has the skew between the individual transmission lines of a parallel transmission bus minimized by the addition of respective load transmission lines to each of the individual transmission lines in the parallel bus. A first circuit unit including a first parallel bank of internal circuits for generating internal control signals is formed adjacent to a predetermined region within a chip. A second circuit unit includes a second parallel bank of internal circuits for performing a predetermined operation in response to an output of the first circuit unit. The second circuit transmits signals to the first circuit over a parallel bus comprised of a plurality of transmission lines connected respectively between the individual internal circuits of the first and second circuit units. A plurality of load transmission lines are connected respectively to predetermined portions of the individual transmission lines to thereby equalize the loads of the transmission lines.

    Abstract translation: 半导体存储器件通过向并行总线中的各个传输线路中的各个传输线路添加相应的负载传输线而使并行传输总线的各个传输线之间的偏移最小化。 在芯片内与预定区域相邻地形成包括用于产生内部控制信号的第一并联的内部电路组的第一电路单元。 第二电路单元包括用于响应于第一电路单元的输出执行预定操作的第二并联的内部电路组。 第二电路通过由分别连接在第一和第二电路单元的各个内部电路之间的多条传输线组成的并行总线向第一电路发送信号。 多个负载传输线分别连接到各个传输线的预定部分，从而均衡传输线的负载。

    Semiconductor memory having a plurality of I/O buses
    26.
    发明授权
    Semiconductor memory having a plurality of I/O buses 失效
    具有多个I / O总线的半导体存储器

    公开(公告)号：US5590086A

    公开(公告)日：1996-12-31

    申请号：US580481

    申请日：1995-12-29

    Applicant: Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

    Inventor： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

    IPC: G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  G11C8/00

    CPC classification number: G11C7/1018 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C2207/2281

    Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

    Abstract translation: 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于 灭活信号在预充电循环中工作。

    Method of outputting temperature data in semiconductor device and temperature data output circuit therefor
    28.
    发明授权
    Method of outputting temperature data in semiconductor device and temperature data output circuit therefor 有权
    在半导体器件中输出温度数据的方法及其温度数据输出电路

    公开(公告)号：US08322922B2

    公开(公告)日：2012-12-04

    申请号：US12605032

    申请日：2009-10-23

    Applicant: Yun-Young Lee ,  Kyu-Chan Lee ,  Ho-Cheol Lee

    Inventor： Yun-Young Lee ,  Kyu-Chan Lee ,  Ho-Cheol Lee

    IPC: G01K7/01 ,  G01K7/14

    CPC classification number: G01K7/015 ,  G01K2219/00

    Abstract: A method of outputting temperature data in a semiconductor device and a temperature data output circuit are provided. A pulse signal is generated in response to a booting enable signal activated in response to a power-up signal and the generation is inactivated in response to a mode setting signal during a power-up operation. A comparison signal is generated in response to the pulse signal by comparing a reference voltage independent of temperature with a sense voltage that varies with temperature change. The temperature data is changed in response to the comparison signal. Thus, the temperature data output circuit can rapidly output the exact temperature of the semiconductor device measured during the power-up operation.

    Abstract translation: 提供了一种在半导体器件和温度数据输出电路中输出温度数据的方法。 响应于响应于上电信号而被激活的引导使能信号而产生脉冲信号，并且响应于上电操作期间的模式设置信号而使生成失效。 通过将与温度无关的参考电压与随温度变化而变化的感测电压进行比较，响应于脉冲信号产生比较信号。 响应于比较信号来改变温度数据。 因此，温度数据输出电路可以快速输出在上电操作期间测量的半导体器件的精确温度。

    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME
    29.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME 审中-公开
    具有它的半导体存储器件和存储器系统

    公开(公告)号：US20120188834A1

    公开(公告)日：2012-07-26

    申请号：US13441713

    申请日：2012-04-06

    Applicant: Ho-Young Kim ,  Ho-Cheol Lee ,  Jung-Bae Lee

    Inventor： Ho-Young Kim ,  Ho-Cheol Lee ,  Jung-Bae Lee

    IPC: G11C7/22

    CPC classification number: G11C7/22 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/222 ,  G11C2207/2272

    Abstract: A semiconductor memory device is disclosed. The semiconductor device includes a memory cell array, a clock signal generator configured to receive an external clock signal from the outside of the memory device and output an internal clock signal, and a data output unit configured to receive an internal data signal from the memory cell array and output a read data signal in response to the internal clock signal. The semiconductor memory device also includes a read data strobe unit configured to output a read data strobe signal having a cycle time of n times (n is an integer equal to or more than 2) a cycle time of the internal clock signal, based on the internal clock signal.

    Abstract translation: 公开了一种半导体存储器件。 半导体器件包括存储单元阵列，时钟信号发生器，被配置为从存储器件的外部接收外部时钟信号并输出​​内部时钟信号;以及数据输出单元，被配置为从存储器单元接收内部数据信号 阵列并响应于内部时钟信号输出读取数据信号。 半导体存储器件还包括读取数据选通单元，其被配置为基于内部时钟信号的周期时间，输出具有n倍（n是等于或大于2的整数）的周期时间的读取数据选通信号 内部时钟信号。

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