公开(公告)号：US09559065B2

公开(公告)日：2017-01-31

申请号：US14476241

申请日：2014-09-03

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Irmgard Escher-Poeppel ,  Juergen Hoegerl ,  Olaf Hohlfeld ,  Peter Kanschat

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L25/07 ,  H01L25/00 ,  H01L23/051 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor arrangement includes upper and lower contact plates and basic chip assemblies. Each chip assembly has a semiconductor chip having a semiconductor body with upper and lower spaced apart sides. An individual upper main electrode and an individual control electrode are arranged on the upper side. The chip assemblies have either respectively a separate lower main electrode arranged on the lower side of the semiconductor chip of the corresponding basic chip assembly, or a common lower main electrode, which for each of the chip assemblies is arranged on the lower side of the semiconductor body of that chip assembly. An electrical current between the individual upper main electrode and the individual or common lower main electrode is controllable by its control electrode. The chip assemblies are connected to one another with a material bonded connection by a dielectric embedding compound, forming a solid assembly.

公开(公告)号：US09275916B2

公开(公告)日：2016-03-01

申请号：US13886283

申请日：2013-05-03

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Irmgard Escher-Poeppel ,  Manfred Engelhardt ,  Hans-Joerg Timme ,  Hannes Eder

IPC: H01L21/66 ,  H01L21/67 ,  H01L21/784 ,  H01L23/00 ,  H01L21/683 ,  H01L21/56

CPC classification number: H01L22/24 ,  H01L21/568 ,  H01L21/67069 ,  H01L21/67253 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/784 ,  H01L22/12 ,  H01L22/26 ,  H01L22/30 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/94 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/82 ,  H01L2924/00

Abstract: A method of processing a plurality of packaged electronic chips being connected to one another in a common substrate is provided, wherein the method comprises etching the electronic chips, detecting information indicative of an at least partial removal of an indicator structure following an exposure of the indicator structure embedded within at least a part of the electronic chips and being exposed after the etching has removed chip material above the indicator structure, and adjusting the processing upon detecting the information indicative of the at least partial removal of the indicator structure.

Abstract translation: 提供一种处理在公共基板中彼此连接的多个封装电子芯片的方法，其中所述方法包括蚀刻所述电子芯片，检测指示在所述指示符的曝光之后至少部分移除指示符结构的信息 嵌入在电子芯片的至少一部分内并且在蚀刻之后暴露出指示器结构之上的芯片材料的结构，以及在检测到指示结构的至少部分移除的信息时调整处理。

公开(公告)号：US20150061100A1

公开(公告)日：2015-03-05

申请号：US14477386

申请日：2014-09-04

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Irmgard Escher-Poeppel ,  Juergen Hoegerl ,  Olaf Hohlfeld ,  Peter Kanschat

IPC: H01L25/07 ,  H01L23/495 ,  H01L23/492 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/072 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L23/051 ,  H01L23/3107 ,  H01L23/48 ,  H01L23/492 ,  H01L23/49562 ,  H01L23/562 ,  H01L24/24 ,  H01L24/33 ,  H01L24/72 ,  H01L24/82 ,  H01L24/83 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/03002 ,  H01L2224/06181 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/29011 ,  H01L2224/32245 ,  H01L2224/82039 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/2064 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2224/03 ,  H01L2224/82 ,  H01L2924/00

Abstract: A semiconductor arrangement includes top and bottom contact plates, a plurality of chip assemblies, a dielectric embedding compound, and a control electrode interconnection structure. Each chip assembly has a semiconductor chip having a semiconductor body. The semiconductor body has a top side and an opposing underside. The top side is spaced apart from the underside in a vertical direction. Each semiconductor chip has a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, a control electrode arranged at the top side, and an electrically conductive top compensation die, arranged on the side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode by means of a top connecting layer. An electric current between the top main electrode and the bottom main electrode can be controlled by means of the control electrode.

Abstract translation: 半导体装置包括顶部和底部接触板，多个芯片组件，电介质嵌入化合物和控制电极互连结构。 每个芯片组件具有半导体芯片，该半导体芯片具有半导体本体。 半导体本体具有顶侧和相对的下侧。 顶侧在垂直方向上与下侧隔开。 每个半导体芯片具有布置在顶侧的顶部主电极，设置在下侧的底部主电极，布置在顶侧的控制电极和布置在顶部主电极对面侧的导电顶部补偿裸片 远离半导体本体并且通过顶部连接层内导电地连接到顶部主电极。 可以通过控制电极来控制顶部主电极和底部主电极之间的电流。

公开(公告)号：US20140264255A1

公开(公告)日：2014-09-18

申请号：US14289512

申请日：2014-05-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Klaus Elian ,  Guenther Ruhl ,  Horst Theuss ,  Irmgard Escher-Poeppel

IPC: H01L29/16

CPC classification number: H01L29/1606 ,  G01N27/127 ,  G01N33/0059 ,  H01L21/561 ,  H01L21/568 ,  H01L23/28 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/315 ,  H01L23/49562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/48 ,  H01L24/49 ,  H01L24/94 ,  H01L24/96 ,  H01L2224/02379 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24011 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/11 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A graphene layer is generated on a substrate. A plastic material is deposited on the graphene layer to at least partially cover the graphene layer. The substrate is separated into at least two substrate pieces.

Abstract translation: 在基板上产生石​​墨烯层。 在石墨烯层上沉积塑料材料以至少部分地覆盖石墨烯层。 将基板分成至少两个基片。

公开(公告)号：US12261146B2

公开(公告)日：2025-03-25

申请号：US18336067

申请日：2023-06-16

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Ralf Otremba ,  Irmgard Escher-Poeppel ,  Martin Gruber

IPC: H01L23/00

Abstract: A semiconductor package is provided. The semiconductor package may include at least one semiconductor chip including a contact pad configured to conduct a current, a conductor element, wherein the conductor element is arranged laterally overlapping the contact pad and with a distance to the contact pad, at least one electrically conductive spacer, a first adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the contact pad, and a second adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the conductor element, wherein the conductor element is electrically conductively connected to a clip or is at least part of a clip, and wherein the spacer is configured to electrically conductively connect the contact pad with the laterally overlapping portion of the conductor element.

公开(公告)号：US11531056B2

公开(公告)日：2022-12-20

申请号：US16849931

申请日：2020-04-15

Applicant: Infineon Technologies AG

Inventor： Irmgard Escher-Poeppel ,  Thorsten Meyer ,  Gerhard Poeppel

IPC: G01R31/26 ,  G01R31/28 ,  G01R31/316 ,  H01L23/60

Abstract: The disclosure describes to techniques for detecting field failures or performance degradation of circuits, including integrated circuits (IC), by including additional contacts, i.e. terminals, along with the functional contacts that used for connecting the circuit to a system in which the circuit is a part. These additional contacts may be used to measure dynamic changing electrical characteristics over time e.g. voltage, current, temperature and impedance. These electrical characteristics may be representative of a certain failure mode and may be an indicator for circuit state-of-health (SOH), while the circuit is performing in the field.

公开(公告)号：US20210325445A1

公开(公告)日：2021-10-21

申请号：US16849931

申请日：2020-04-15

Applicant: Infineon Technologies AG

Inventor： Irmgard Escher-Poeppel ,  Thorsten Meyer ,  Gerhard Poeppel

IPC: G01R31/26 ,  G01R31/28 ,  G01R31/316 ,  H01L23/60

Abstract: The disclosure describes to techniques for detecting field failures or performance degradation of circuits, including integrated circuits (IC), by including additional contacts, i.e. terminals, along with the functional contacts that used for connecting the circuit to a system in which the circuit is a part. These additional contacts may be used to measure dynamic changing electrical characteristics over time e.g. voltage, current, temperature and impedance. These electrical characteristics may be representative of a certain failure mode and may be an indicator for circuit state-of-health (SOH), while the circuit is performing in the field.

公开(公告)号：US10734352B2

公开(公告)日：2020-08-04

申请号：US16148316

申请日：2018-10-01

Applicant: Infineon Technologies AG

Inventor： Irmgard Escher-Poeppel ,  Khalil Hosseini ,  Johannes Lodermeyer ,  Joachim Mahler ,  Thorsten Meyer ,  Georg Meyer-Berg ,  Ivan Nikitin ,  Reinhard Pufall ,  Edmund Riedl ,  Klaus Schmidt ,  Manfred Schneegans ,  Patrick Schwarz

IPC: H01L23/00

Abstract: A metallic interconnection and a semiconductor arrangement including the same are described, wherein a method of manufacturing the same may include: providing a first structure including a first metallic layer having protruding first microstructures; providing a second structure including a second metallic layer having protruding second microstructures; contacting the first and second microstructures to form a mechanical connection between the structures, the mechanical connection being configured to allow fluid penetration; removing one or more non-metallic compounds on the first metallic layer and the second metallic layer with a reducing agent that penetrates the mechanical connection and reacts with the one or more non-metallic compounds; and heating the first metallic layer and the second metallic layer at a temperature causing interdiffusion of the first metallic layer and the second metallic layer to form the metallic interconnection between the structures.

公开(公告)号：US09818730B2

公开(公告)日：2017-11-14

申请号：US14477386

申请日：2014-09-04

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Irmgard Escher-Poeppel ,  Juergen Hoegerl ,  Olaf Hohlfeld ,  Peter Kanschat

IPC: H01L23/48 ,  H01L25/07 ,  H01L23/492 ,  H01L23/495 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L23/051 ,  H01L23/31

CPC classification number: H01L25/072 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L23/051 ,  H01L23/3107 ,  H01L23/48 ,  H01L23/492 ,  H01L23/49562 ,  H01L23/562 ,  H01L24/24 ,  H01L24/33 ,  H01L24/72 ,  H01L24/82 ,  H01L24/83 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/03002 ,  H01L2224/06181 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/29011 ,  H01L2224/32245 ,  H01L2224/82039 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/2064 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2224/03 ,  H01L2224/82 ,  H01L2924/00

Abstract: A semiconductor arrangement includes top and bottom contact plates, a plurality of chip assemblies, a dielectric embedding compound, and a control electrode interconnection structure. Each chip assembly has a semiconductor chip having a semiconductor body. The semiconductor body has a top side and an opposing underside. The top side is spaced apart from the underside in a vertical direction. Each semiconductor chip has a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, a control electrode arranged at the top side, and an electrically conductive top compensation die, arranged on the side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode by means of a top connecting layer. An electric current between the top main electrode and the bottom main electrode can be controlled by means of the control electrode.

公开(公告)号：US20150287788A1

公开(公告)日：2015-10-08

申请号：US14745428

申请日：2015-06-20

Applicant: Infineon Technologies AG

Inventor： Klaus Elian ,  Guenther Ruhl ,  Horst Theuss ,  Irmgard Escher-Poeppel

IPC: H01L29/16 ,  H01L23/00 ,  H01L23/495 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L29/1606 ,  G01N27/127 ,  G01N33/0059 ,  H01L21/561 ,  H01L21/568 ,  H01L23/28 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/315 ,  H01L23/49562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/48 ,  H01L24/49 ,  H01L24/94 ,  H01L24/96 ,  H01L2224/02379 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24011 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/11 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A graphene layer is generated on a substrate. A plastic material is deposited on the graphene layer to at least partially cover the graphene layer. The substrate is separated into at least two substrate pieces.

Abstract translation: 在基板上产生石​​墨烯层。 在石墨烯层上沉积塑料材料以至少部分地覆盖石墨烯层。 将基板分成至少两个基片。