公开(公告)号：US20200273790A1

公开(公告)日：2020-08-27

申请号：US16748049

申请日：2020-01-21

Applicant: Infineon Technologies AG

Inventor： Bun Kian Tay ,  Mei Yih Goh ,  Martin Gruber ,  Josef Hoeglauer ,  Michael Juerss ,  Josef Maerz ,  Thorsten Meyer ,  Thorsten Scharf ,  Chee Voon Tan

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56

Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.

公开(公告)号：US20190148332A1

公开(公告)日：2019-05-16

申请号：US15811375

申请日：2017-11-13

Applicant: Infineon Technologies AG

Inventor： Eung San Cho ,  Thorsten Meyer ,  Xaver Schloegel ,  Thomas Behrens ,  Josef Hoeglauer

IPC: H01L23/00 ,  H01L23/498

Abstract: In some examples, a device includes a semiconductor element, a layer element, and a single connector element electrically connecting the semiconductor element and the layer element. In some examples, the single connector element includes two or more discrete connector elements, and each discrete connector element of the two or more discrete connector elements electrically connects the semiconductor element and the layer element. In some examples, the single connector element also includes conductive material attached to the two or more discrete connector elements.

公开(公告)号：US09627292B2

公开(公告)日：2017-04-18

申请号：US14036110

申请日：2013-09-25

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Xaver Schloegel ,  Juergen Schredl

IPC: H01L23/40 ,  H01L21/50 ,  H01L23/495

CPC classification number: H01L23/4006 ,  H01L21/50 ,  H01L23/49562 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor housing includes a fixing mechanism and at least one side having structurings. A method for producing a semiconductor device is provided in which a thermally conductive paste is applied on the at least one side of the semiconductor housing and/or of a heat sink. The semiconductor housing is fixed to the heat sink by means of the fixing mechanism. A pressure is exerted on the thermally conductive paste by means of the fixing mechanism and the thermally conductive paste is diverted by means of diversion channels depending on the pressure exerted.

公开(公告)号：US09449902B2

公开(公告)日：2016-09-20

申请号：US14535138

申请日：2014-11-06

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Juergen Schredl ,  Xaver Schloegel ,  Klaus Schiess

IPC: H01L29/76 ,  H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L29/20 ,  H01L29/78

CPC classification number: H01L23/49562 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49568 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L29/2003 ,  H01L29/78 ,  H01L2224/05552 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/40245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/85207 ,  H01L2224/85801 ,  H01L2224/8585 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/12031 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00012

Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a first lead frame having a first die paddle, and a second lead frame, which has a second die paddle and a plurality of leads. The second die paddle is disposed over the first die paddle. A semiconductor chip is disposed over the second die paddle. The semiconductor chip has a plurality of contact regions on a first side facing the second lead frame. The plurality of contact regions is coupled to the plurality of leads.

Abstract translation: 根据本发明的实施例，半导体封装包括具有第一管芯焊盘的第一引线框架和具有第二管芯焊盘和多个引线的第二引线框架。 第二模板设置在第一模板上。 半导体芯片设置在第二裸片上。 半导体芯片在面向第二引线框架的第一面上具有多个接触区域。 多个接触区域耦合到多个引线。

公开(公告)号：US20150279782A1

公开(公告)日：2015-10-01

申请号：US14735604

申请日：2015-06-10

Applicant: Infineon Technologies AG

Inventor： Henrik Ewe ,  Joachim Mahler ,  Manfred Mengel ,  Reimund Engl ,  Josef Hoeglauer ,  Jochen Dangelmaier

IPC: H01L23/538 ,  H01L23/495 ,  H01L21/288 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/5389 ,  H01L21/02282 ,  H01L21/02288 ,  H01L21/288 ,  H01L21/31105 ,  H01L21/4821 ,  H01L21/6835 ,  H01L21/76801 ,  H01L21/76871 ,  H01L21/76877 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49534 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L2221/68345 ,  H01L2224/24011 ,  H01L2224/2402 ,  H01L2224/24051 ,  H01L2224/24137 ,  H01L2224/24145 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2224/24998 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82001 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/82102 ,  H01L2225/06568 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19043 ,  H01L2924/00 ,  H05K3/4661

Abstract: A semiconductor device is disclosed. One embodiment includes a carrier, a semiconductor chip attached to the carrier, a first conducting line having a first thickness and being deposited over the semiconductor chip and the carrier and a second conducting line having a second thickness and being deposited over the semiconductor chip and the carrier. The first thickness is smaller than the second thickness.

公开(公告)号：US20140084449A1

公开(公告)日：2014-03-27

申请号：US14036110

申请日：2013-09-25

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Xaver Schloegel ,  Juergen Schredl

IPC: H01L23/40 ,  H01L21/50

CPC classification number: H01L23/4006 ,  H01L21/50 ,  H01L23/49562 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor housing includes a fixing mechanism and at least one side having structurings. A method for producing a semiconductor device is provided in which a thermally conductive paste is applied on the at least one side of the semiconductor housing and/or of a heat sink. The semiconductor housing is fixed to the heat sink by means of the fixing mechanism. A pressure is exerted on the thermally conductive paste by means of the fixing mechanism and the thermally conductive paste is diverted by means of diversion channels depending on the pressure exerted.

Abstract translation: 半导体外壳包括固定机构和具有结构的至少一个侧面。 提供一种制造半导体器件的方法，其中在半导体外壳和/或散热器的至少一侧上施加导热膏。 半导体外壳借助固定机构固定在散热片上。 通过固定机构对导热性浆料施加压力，导热膏根据所施加的压力利用引流通道而转向。

公开(公告)号：US12205919B2

公开(公告)日：2025-01-21

申请号：US17555709

申请日：2021-12-20

Applicant: Infineon Technologies AG

Inventor： Chuan Cheah ,  Josef Hoeglauer ,  Tobias Polster

IPC: H01L21/78 ,  H01L21/56 ,  H01L23/00 ,  H01L23/373 ,  H01L23/538 ,  H01L25/00 ,  H01L25/07 ,  H01L29/40 ,  H01L29/45

Abstract: A method of processing a semiconductor wafer includes: forming an electronic device at each die location of the semiconductor wafer; partially forming a frontside metallization over a frontside of the semiconductor wafer at each die location; partially forming a backside metallization over a backside of the semiconductor wafer at each die location; and after partially forming both the frontside metallization and the backside metallization but without completing either the frontside metallization or the backside metallization, singulating the semiconductor wafer between the die locations to form a plurality of individual semiconductor dies, wherein the partially formed frontside metallization and the partially formed backside metallization have a same composition. Semiconductor dies and methods of producing semiconductor modules are also described.

公开(公告)号：US12027436B2

公开(公告)日：2024-07-02

申请号：US17575038

申请日：2022-01-13

Applicant: Infineon Technologies AG

Inventor： Angela Kessler ,  Kok Yau Chua ,  Josef Hoeglauer ,  Chiah Chin Lim ,  Mei Qi Tay

IPC: H01L29/06 ,  H01L21/52 ,  H01L23/31 ,  H01L23/495 ,  H01L23/538 ,  H01L31/072 ,  H01L31/109

CPC classification number: H01L23/3157 ,  H01L21/52 ,  H01L23/49541 ,  H01L23/5384

Abstract: A package and method of manufacturing is disclosed. In one example, the package which comprises a carrier with at least one component mounted on the carrier. A clip is arranged above the carrier and having a through hole. At least part of at least one of the at least one component and/or at least part of an electrically conductive connection element electrically connecting the at least one component is at least partially positioned inside the through hole.

公开(公告)号：US20230197663A1

公开(公告)日：2023-06-22

申请号：US17555709

申请日：2021-12-20

Applicant: Infineon Technologies AG

Inventor： Chuan Cheah ,  Josef Hoeglauer ,  Tobias Polster

IPC: H01L23/00 ,  H01L21/78 ,  H01L29/40 ,  H01L21/56 ,  H01L25/00 ,  H01L25/07 ,  H01L23/538

CPC classification number: H01L24/24 ,  H01L21/78 ,  H01L29/401 ,  H01L21/568 ,  H01L24/82 ,  H01L25/50 ,  H01L25/072 ,  H01L23/5389 ,  H01L29/45

Abstract: A method of processing a semiconductor wafer includes: forming an electronic device at each die location of the semiconductor wafer; partially forming a frontside metallization over a frontside of the semiconductor wafer at each die location; partially forming a backside metallization over a backside of the semiconductor wafer at each die location; and after partially forming both the frontside metallization and the backside metallization but without completing either the frontside metallization or the backside metallization, singulating the semiconductor wafer between the die locations to form a plurality of individual semiconductor dies, wherein the partially formed frontside metallization and the partially formed backside metallization have a same composition. Semiconductor dies and methods of producing semiconductor modules are also described.

公开(公告)号：US20200273781A1

公开(公告)日：2020-08-27

申请号：US16282207

申请日：2019-02-21

Applicant: Infineon Technologies AG

Inventor： Thorsten Scharf ,  Martin Gruber ,  Josef Hoeglauer ,  Michael Juerss ,  Josef Maerz ,  Thorsten Meyer ,  Bun Kian Tay

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56

Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.