公开(公告)号：US20170358494A1

公开(公告)日：2017-12-14

申请号：US15182387

申请日：2016-06-14

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Manfred Engelhardt ,  Gudrun Stranzl

IPC: H01L21/78 ,  H01L21/3065 ,  H01J37/32 ,  H01L29/16 ,  H01L23/495 ,  H01L21/67

CPC classification number: H01L21/78 ,  H01J37/32009 ,  H01J37/32091 ,  H01J37/3244 ,  H01J37/32724 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/67069 ,  H01L21/67109 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49562 ,  H01L29/1608 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A method of forming a semiconductor device includes forming an active region in a first side of a silicon carbide substrate, the silicon carbide substrate having a second side opposite the first side and forming a contact pad at the first side. The contact pad is coupled to the active region. The method further includes forming an etch stop layer over the contact pad and plasma dicing the silicon carbide substrate from the second side. The plasma dicing etches through the silicon carbide substrate and stops on the etch stop layer. The diced silicon carbide substrate is held together by the etch stop layer. The diced silicon carbide substrate is attached on a carrier. The diced silicon carbide substrate is separated into silicon carbide dies by cleaving the etch stop layer.

公开(公告)号：US20170076970A1

公开(公告)日：2017-03-16

申请号：US15359620

申请日：2016-11-23

Applicant: Infineon Technologies AG

Inventor： Gudrun Stranzl ,  Martin Zgaga ,  Rainer Leuschner ,  Bernhard Goller ,  Bernhard Boche ,  Manfred Engelhardt ,  Hermann Wendt ,  Bernd Noehammer ,  Karl Mayer ,  Michael Roesner ,  Monika Cornelia Voerckel

IPC: H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L21/285 ,  H01L21/304 ,  H01L21/033 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L21/6835 ,  H01L21/0331 ,  H01L21/283 ,  H01L21/2855 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/6836 ,  H01L21/76895 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/0001

Abstract: Methods for processing a semiconductor workpiece can include providing a semiconductor workpiece that includes one or more kerf regions; forming one or more trenches in the workpiece by removing material from the one or more kerf regions from a first side of the workpiece; mounting the workpiece with the first side to a carrier; thinning the workpiece from a second side of the workpiece; and forming a metallization layer over the second side of the workpiece.

Abstract translation: 用于处理半导体工件的方法可以包括提供包括一个或多个切口区域的半导体工件; 通过从所述工件的第一侧移除来自所述一个或多个切割区域的材料，在所述工件中形成一个或多个沟槽; 将具有第一侧的工件安装到载体上; 从工件的第二侧使工件变薄; 以及在所述工件的第二侧上形成金属化层。

公开(公告)号：US20160343574A1

公开(公告)日：2016-11-24

申请号：US14717780

申请日：2015-05-20

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt ,  Michael Roesner ,  Georg Ehrentraut

IPC: H01L21/3065 ,  H01L29/06 ,  H01L21/78

CPC classification number: H01L21/3065 ,  H01J37/32642 ,  H01J37/32651 ,  H01L21/67092 ,  H01L21/78

Abstract: A segmented edge protection shield for plasma dicing a wafer. The segmented edge protection shield includes an outer structure and a plurality of plasma shield edge segments. The outer structure defines an interior annular edge configured to correspond to the circumferential edge of the wafer. Each one of the plurality of plasma shield edge segments is defined by an inner edge and side edges. The inner edge is interior to and concentric to the annular edge of the outer structure. The side edges extend between the inner edge and the annular edge.

Abstract translation: 用于等离子体切割晶片的分段边缘保护屏蔽。 分段边缘保护屏蔽包括外部结构和多个等离子体屏蔽边缘段。 外部结构限定了内部环形边缘，其构造成对应于晶片的周边边缘。 多个等离子体屏蔽边缘段中的每一个由内边缘和侧边缘限定。 内边缘位于外部结构的环形边缘的内部并与其同心。 侧边缘在内边缘和环形边缘之间延伸。

公开(公告)号：US09455192B2

公开(公告)日：2016-09-27

申请号：US14226666

申请日：2014-03-26

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Manfred Engelhardt ,  Johann Schmid ,  Gudrun Stranzl ,  Joachim Hirschler

IPC: H01L21/46 ,  H01L21/78 ,  H01L21/768 ,  H01L23/00 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/7806 ,  H01L21/02057 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/76879 ,  H01L21/76898 ,  H01L21/78 ,  H01L24/32 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2924/10157 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/00014 ,  H01L2924/00

Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes attaching a substrate to a carrier using an adhesive component and forming a through trench through the substrate to expose the adhesive component. At least a portion of the adhesive component is etched and a metal layer is formed over sidewalls of the through trench.

Abstract translation: 根据本发明的实施例，一种形成半导体器件的方法包括：使用粘合剂组件将衬底附着到载体上，并通过衬底形成通孔以暴露粘合剂组分。 蚀刻粘合剂组分的至少一部分，并且在通孔的侧壁上形成金属层。

公开(公告)号：US20230317666A1

公开(公告)日：2023-10-05

申请号：US17712738

申请日：2022-04-04

Applicant: Infineon Technologies AG

Inventor： Gregor Langer ,  Michael Roesner ,  Ewald Wiltsche ,  Ronny Kern ,  Victorina Poenariu ,  Axel Koenig

IPC: H01L23/00 ,  H01L29/16

CPC classification number: H01L24/27 ,  H01L29/1608 ,  H01L2224/27848 ,  H01L2224/29155 ,  H01L2924/048 ,  H01L24/29

Abstract: A semiconductor device and a method of manufacturing a semiconductor are provided. In an embodiment, a method of manufacturing a semiconductor device is provided. A first layer is formed over a silicon carbide (SiC) layer. The first layer has a first surface distal the SiC layer and a second surface proximal the SiC layer. The first layer includes a metal. First thermal energy may be directed to the first surface of the first layer to form a metal silicide layer from the metal of the first layer and silicon of the SiC layer. The metal silicide layer has a first surface distal the SiC layer and a second surface proximal the SiC layer. Second thermal energy may be directed to the first surface of the metal silicide layer to reduce a surface roughness of the first surface of the metal silicide layer

公开(公告)号：US11367654B2

公开(公告)日：2022-06-21

申请号：US16248255

申请日：2019-01-15

Applicant: Infineon Technologies AG

Inventor： Karl Mayer ,  Evelyn Napetschnig ,  Michael Pinczolits ,  Michael Sternad ,  Michael Roesner

IPC: H01L21/78 ,  H01L23/544 ,  H01L23/48 ,  H01L23/58 ,  H01L23/00 ,  H01L23/31

Abstract: A system and method for manufacturing a packaged component are disclosed. An embodiment comprises forming a plurality of components on a carrier, the plurality of components being separated from each other by kerf regions on a front side of the carrier and forming a metal pattern on a backside of the carrier, wherein the metal pattern covers the backside of the carrier except over regions corresponding to the kerf regions. The method further comprises generating the component by separating the carrier.

公开(公告)号：US11195713B2

公开(公告)日：2021-12-07

申请号：US16426051

申请日：2019-05-30

Applicant: Infineon Technologies AG

Inventor： Joachim Hirschler ,  Georg Ehrentraut ,  Christoffer Erbert ,  Klaus Goeschl ,  Markus Heinrici ,  Michael Hutzler ,  Wolfgang Koell ,  Stefan Krivec ,  Ingmar Neumann ,  Mathias Plappert ,  Michael Roesner ,  Olaf Storbeck

IPC: H01L21/02 ,  H01L29/51 ,  H01L21/28 ,  H01L21/18 ,  H01L29/49

Abstract: In one aspect, a method of forming a silicon-insulator layer is provided. The method includes arranging a silicon structure in a plasma etch process chamber and applying a plasma to the silicon structure in the plasma etch process chamber at a temperature of the silicon structure equal to or below 100° C. The plasma includes a component and a halogen derivate, thereby forming the silicon-insulator layer. The silicon-insulator layer includes silicon and the component. In another aspect, a semiconductor device is provided having a silicon-insulator layer formed by the method.

公开(公告)号：US20190308274A1

公开(公告)日：2019-10-10

申请号：US16374265

申请日：2019-04-03

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Markus Menath ,  Gudrun Stranzl

IPC: B23K26/362 ,  B23K26/40 ,  H01L21/67 ,  H01L21/3065 ,  H01L29/16

Abstract: A method of processing silicon carbide containing crystalline substrate is provided. The method includes pyrolyzing a surface of the silicon carbide containing crystalline substrate to produce a silicon and carbon containing debris layer over the silicon carbide containing crystalline substrate, and removing the silicon and carbon containing debris layer, wherein the pyrolyzing and the removing is repeated at least once.

公开(公告)号：US20190295981A1

公开(公告)日：2019-09-26

申请号：US16360570

申请日：2019-03-21

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Markus Menath ,  Gudrun Stranzl

IPC: H01L23/00 ,  H01L29/16 ,  H01L29/45 ,  H01L21/04

Abstract: A semiconductor device includes a silicon carbide layer, a metal carbide layer arranged over the silicon carbide layer, and a solder layer arranged over and in contact with the metal carbide layer.

公开(公告)号：US10005659B2

公开(公告)日：2018-06-26

申请号：US15440962

申请日：2017-02-23

Applicant: Infineon Technologies AG

Inventor： Thomas Grille ,  Ursula Hedenig ,  Michael Roesner ,  Gudrun Stranzl ,  Martin Zgaga

IPC: B81B7/00 ,  B01D67/00 ,  B81C1/00

CPC classification number: B81B7/0061 ,  B01D67/0034 ,  B81B2201/0257 ,  B81B2201/10 ,  B81C1/00904 ,  B81C2201/0132 ,  Y10T428/24273

Abstract: A hole plate and a MEMS microphone arrangement are disclosed. In an embodiment a hole plate includes a substrate with a first main surface, a second main surface, and a lateral surface and a perforation structure formed within the substrate, the perforation structure having a plurality of through-holes through the substrate, wherein the through-holes and the lateral surface are a result of a simultaneous dry etching step.