公开(公告)号：US20170188455A1

公开(公告)日：2017-06-29

申请号：US14998263

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Yoshihiro Tomita ,  Joshua D. Heppner ,  Shawna M. Liff ,  Pramod Malatkar

IPC: H05K1/03 ,  H05K1/18 ,  A41D13/00 ,  H05K3/00 ,  A41D1/00 ,  A43B3/00 ,  H05K1/11 ,  H05K3/32

CPC classification number: H05K1/0393 ,  A41D1/002 ,  A41D13/0015 ,  A43B1/0054 ,  A43B3/0005 ,  H05K1/03 ,  H05K1/118 ,  H05K1/189 ,  H05K3/0011 ,  H05K3/007 ,  H05K3/32 ,  H05K2201/0129 ,  H05K2201/0203 ,  H05K2201/0215 ,  H05K2201/08 ,  H05K2201/083 ,  H05K2203/0152 ,  H05K2203/104

Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing a magnetic particle embedded flexible substrate, a printed flexible substrate for a magnetic tray, or an electro-magnetic carrier for magnetized or ferromagnetic flexible substrates. For instance, in accordance with one embodiment, there are means disclosed for fabricating a flexible substrate having one or more electrical interconnects to couple with leads of an electrical device; integrating magnetic particles or ferromagnetic particles into the flexible substrate; supporting the flexible substrate with a carrier plate during one or more manufacturing processes for the flexible substrate, in which the flexible substrate is held flat against the carrier plate by an attractive magnetic force between the magnetic particles or ferromagnetic particles integrated with the flexible substrate and a complementary magnetic attraction of the carrier plate; and removing the flexible substrate from the carrier plate subsequent to completion of the one or more manufacturing processes for the flexible substrate. Other related embodiments are disclosed.

公开(公告)号：US09615483B2

公开(公告)日：2017-04-04

申请号：US14484896

申请日：2014-09-12

Applicant: Intel Corporation

Inventor： Gaurav Chawla ,  Joshua D. Heppner ,  Vijaykumar Krithivasan ,  Michael Garcia ,  Kuang C. Liu ,  Rajasekaran Swaminathan

IPC: H05K7/20 ,  H01L23/367 ,  H01L23/40 ,  H01L23/433

CPC classification number: H05K7/20 ,  H01L23/3675 ,  H01L23/4006 ,  H01L23/433 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed toward techniques and configurations associated with a package load assembly. In one embodiment, a package load assembly may include a frame configured to form a perimeter around a die area of a package substrate having a first surface configured to be coupled with a surface of the package substrate and a second surface disposed opposite to the first surface. The frame may include deformable members disposed on the second surface, which may be configured to be coupled with a base of a heat sink to distribute force applied between the heat sink and the package substrate, via the frame, and may deform under application of the force, which may allow the base of the heat sink to contact a surface of an integrated heat spreader within the die area of the package substrate.

公开(公告)号：US20150249298A1

公开(公告)日：2015-09-03

申请号：US14563641

申请日：2014-12-08

Applicant: Intel Corporation

Inventor： Gaurav Chawla ,  Joshua D. Heppner ,  Zhichao Zhang ,  David J. Llapitan ,  Vijaykumar Krithivasan

IPC: H01R12/72 ,  H01R12/70 ,  H01L23/34 ,  H01R13/11

CPC classification number: H01R12/722 ,  H01L23/34 ,  H01L2924/0002 ,  H01R12/7005 ,  H01R12/71 ,  H01R12/724 ,  H01R12/79 ,  H01R13/114 ,  H01L2924/00

Abstract: Connectors and methods to couple packages and dies are shown. Selected examples include plugs and receptacles having two or more terraces with contacts provided along the terraces. Examples of connectors and methods include configurations where the connector is usable with a package including a die coupled along a substrate. In selected examples a heat sink is coupled over the die, and a package includes a side access port between the heat sink and the substrate configured to receive the connector, such as one or more of a plug or receptacle through the side access port.

Abstract translation: 显示连接器和耦合封装和管芯的方法。 所选择的示例包括具有两个或更多台阶的插头和插座，其具有沿着梯田提供的触点。 连接器和方法的示例包括其中连接器可用于包括沿衬底耦合的裸片的封装的配置。 在所选择的示例中，散热器耦合在管芯上，并且封装包括在散热器和被配置为接收连接器的基板之间的侧入口，例如通过侧面接入端口的一个或多个插头或插座。

公开(公告)号：US20210307189A1

公开(公告)日：2021-09-30

申请号：US17251697

申请日：2018-12-21

Applicant: Intel Corporation

Inventor： Chris D. Lucero ,  Khine Han ,  Joshua D. Heppner ,  Christopher Rossi ,  Hadi Sharifi ,  Aniekeme Udofia ,  Abdul Bailey ,  Katherine Perkins ,  Kevin Lowell Hudson ,  Roderick E. Kronschnabel ,  Neha Purushothaman

IPC: H05K7/14 ,  G06F15/78 ,  H05K1/14

Abstract: In some examples, an Internet of Things (IoT) apparatus including a plurality of boards and one or more connectors to couple IoT modules to one or more of the plurality of boards and to couple the plurality of boards to each other. The connectors include stacking connectors on both sides of at least some of the boards and at least some of the IoT modules to be coupled to the boards. The stacking connectors allow the IoT modules and the boards to be coupled together in a manner that boards and modules cannot be inserted incorrectly.

公开(公告)号：US10825714B2

公开(公告)日：2020-11-03

申请号：US15089480

申请日：2016-04-02

Applicant: INTEL CORPORATION

Inventor： Daniel Chavez-Clemente ,  Joshua D. Heppner ,  Naida Duranovic

IPC: H01L21/687 ,  H01L23/00 ,  H01L23/538

Abstract: A substrate retention plate system for holding a substrate for processing in an electronic device manufacturing process is described. The retention plate system includes a top plate and a bottom plate to sandwich a flexible substrate. Additionally, the top plate includes a number of cams to stretch the flexible substrate across the bottom plate.

公开(公告)号：US10820437B2

公开(公告)日：2020-10-27

申请号：US16335050

申请日：2016-09-28

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Son V. Nguyen ,  Rajat Goyal ,  David B. Lampner ,  Dilan Seneviratne ,  Albert S. Lopez ,  Joshua D. Heppner ,  Srinivas V. Pietambaram ,  Shawna M. Liff ,  Nadine L. Dabby

IPC: G06F17/30 ,  H05K5/06 ,  H05K5/00 ,  H05K5/02 ,  G06F1/18 ,  G06F1/16 ,  G04G17/04

Abstract: The document discloses a stretchable packaging system for a wearable electronic device. The system includes a first electronic component and a flexible trace connected to the first electronic component. An elastomer layer having a variable thickness at least partially encapsulates the first electronic component and the flexible trace. A first region of the layer has a first thickness that is greater than a second thickness of a second region of the layer that at least partially encapsulates the trace.

公开(公告)号：US10672625B2

公开(公告)日：2020-06-02

申请号：US16083611

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Sergio A. Chan Arguedas ,  Joshua D. Heppner ,  Jimin Yao

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/13 ,  H01L23/15 ,  H01L23/14

Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate having a recess, an electronic component disposed in the recess and electrically coupled to the substrate, and an underfill material disposed in the recess between the electronic component and the substrate. Associated systems and methods are also disclosed.

公开(公告)号：US10111368B2

公开(公告)日：2018-10-23

申请号：US14973510

申请日：2015-12-17

Applicant: Intel Corporation

Inventor： Yoshihiro Tomita ,  Joshua D. Heppner

IPC: H01L51/00 ,  H05K13/00 ,  H01L23/40 ,  H05K3/32 ,  B23P19/04 ,  H05K1/03 ,  H01L23/544 ,  H01L23/498

Abstract: Systems to manufacture an electronic circuit assembly are disclosed. In one embodiment, the system includes a flexible substrate with a substrate registration feature and a carrier with a carrier registration feature. A removable fastener removably fixes the flexible substrate to the carrier by being received into the substrate registration feature and the carrier registration feature. Once the flexible substrate is removably affixed to the carrier, the carrier provides the flexible substrate with rigidity to receive at least one electronic device of the electronic circuit assembly.

公开(公告)号：US20180019193A1

公开(公告)日：2018-01-18

申请号：US15212951

申请日：2016-07-18

Applicant: Intel Corporation

Inventor： Zuyang Liang ,  Michael Garcia ,  Joshua D. Heppner ,  Srikant Nekkanty

IPC: H01L23/498 ,  H01L23/13

CPC classification number: H01L23/49816 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49827 ,  H01R13/2485

Abstract: Embodiments herein may relate to an electronic device that includes a board. The electronic device may include a device physically coupled with the board by an anchoring pin. The electronic device may further include a plurality of ball grid array (BGA) solder joints coupled with the device. For example, the BGA solder joints may electrically and/or communicatively couple one or more pins of the device with the board. The BGA solder joints may have a shape that is different than the anchoring pin. Other embodiments may be described and/or claimed.

公开(公告)号：US09780510B2

公开(公告)日：2017-10-03

申请号：US14764931

申请日：2014-09-26

Applicant: INTEL CORPORATION

Inventor： Dhanya Athreya ,  Gaurav Chawla ,  Kemal Aygun ,  Glen P. Gordon ,  Sarah M. Canny ,  Jeffory L. Smalley ,  Srikant Nekkanty ,  Michael Garcia ,  Joshua D. Heppner

IPC: H01R24/00 ,  H01R33/76 ,  H01L23/32 ,  H01L23/498

CPC classification number: H01R33/7685 ,  H01L23/32 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards socket contact techniques and configurations. In one embodiment, an apparatus may include a socket substrate having a first side and a second side disposed opposite to the first side, an opening formed through the socket substrate, an electrical contact disposed in the opening and configured to route electrical signals between the first side and the second side of the socket substrate, the electrical contact having a cantilever portion that extends beyond the first side, wherein the first side and surfaces of the socket substrate in the opening are plated with a metal. Other embodiments may be described and/or claimed.