公开(公告)号：US20240063202A1

公开(公告)日：2024-02-22

申请号：US17820968

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Thomas Sounart ,  Henning Braunisch ,  William J. Lambert ,  Kaladhar Radhakrishnan ,  Shawna M. Liff ,  Mohammad Enamul Kabir ,  Omkar G. Karhade ,  Kimin Jun ,  Johanna M. Swan

IPC: H01L25/18 ,  H01L23/522 ,  H01L49/02 ,  H01L23/00 ,  H01L23/498 ,  H01L23/48 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L23/5223 ,  H01L28/90 ,  H01L24/08 ,  H01L23/49811 ,  H01L23/481 ,  H01L25/50 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Embodiments of a microelectronic assembly comprise: a plurality of layers of IC dies in a dielectric material, adjacent layers in the plurality of layers being coupled together by first interconnects having a pitch of less than 10 micrometers between adjacent first interconnects; a package substrate coupled to a first side of the plurality of layers by second interconnects; a support structure coupled to a second side of the plurality of layers by third interconnects, the second side being opposite to the first side; and capacitors in at least the plurality of layers or the support structure. The capacitors are selected from at least planar capacitors, deep trench capacitors and via capacitors.

公开(公告)号：US20240063066A1

公开(公告)日：2024-02-22

申请号：US17891665

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Tomita Yoshihiro ,  Adel A. Elsherbini ,  Bhaskar Jyoti Krishnatreya ,  Tushar Talukdar ,  Haris Khan Niazi ,  Yi Shi ,  Batao Zhang ,  Wenhao Li ,  Feras Eid

IPC: H01L23/04 ,  H01L25/065 ,  H01L23/18 ,  H01L23/00 ,  H01L23/48 ,  H01L23/46 ,  H01L23/367

CPC classification number: H01L23/041 ,  H01L25/0652 ,  H01L23/18 ,  H01L24/08 ,  H01L23/481 ,  H01L23/46 ,  H01L23/367 ,  H01L2224/08145 ,  H01L2224/05599 ,  H01L24/05 ,  H01L2224/80379 ,  H01L24/80 ,  H01L2224/16227 ,  H01L24/16 ,  H01L2224/32225 ,  H01L24/32 ,  H01L2224/73204 ,  H01L24/73 ,  H01L2224/131 ,  H01L24/13 ,  H01L2224/29099 ,  H01L24/29

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a surface; a template structure having a first surface and an opposing second surface, wherein the first surface of the template structure is coupled to the surface of the first die, and wherein the template structure includes a cavity at the first surface and a through-template opening extending from a top surface of the cavity to the second surface of the template structure; and a second die within the cavity of the template structure and electrically coupled to the surface of the first die by interconnects having a pitch of less than 10 microns between adjacent interconnects.

公开(公告)号：US20240006395A1

公开(公告)日：2024-01-04

申请号：US17853778

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Debendra Mallik ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Nitin A. Deshpande ,  Omkar G. Karhade ,  Ravindranath Vithal Mahajan ,  Abhishek A. Sharma

IPC: H01L25/16 ,  H01L23/492 ,  H01L23/522 ,  H01L23/528 ,  H01L23/04 ,  H01L23/46 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L25/167 ,  H01L23/492 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/04 ,  H01L2224/80895 ,  H01L23/481 ,  H01L24/08 ,  H01L24/80 ,  H01L24/96 ,  H01L2224/08146 ,  H01L23/46

Abstract: Embodiments of a microelectronic assembly comprise: a plurality of microelectronic sub-assemblies arranged in a coplanar array, each microelectronic sub-assembly having a first side and an opposing second side; a first conductive plate coupled to the first sides of the microelectronic sub-assemblies; and a second conductive plate coupled to the second sides of the microelectronic sub-assemblies. The first conductive plate and the second conductive plate comprise sockets corresponding to each of the microelectronic sub-assemblies, and each microelectronic sub-assembly comprises a first plurality of integrated circuit (IC) dies coupled on one end to a first IC die and on an opposing end to a second IC die; and a second plurality of IC dies coupled to the first IC die and to the second IC die.

公开(公告)号：US20230420410A1

公开(公告)日：2023-12-28

申请号：US17846129

申请日：2022-06-22

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Omkar G. Karhade ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma ,  Tahir Ghani ,  Anand S. Murthy ,  Nitin A. Deshpande

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/522 ,  H01L23/46 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L24/08 ,  H01L23/5226 ,  H01L23/46 ,  H01L24/94 ,  H01L24/96 ,  H01L25/50 ,  H01L24/80 ,  H01L2224/08137 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Embodiments of an integrated circuit (IC) die comprise: a first IC die coupled to at least two second IC dies by interconnects on a first surface of the first IC die and second surfaces of the second IC dies such that the first surface is in contact with the second surfaces. The second surfaces are coplanar, the interconnects comprise dielectric-dielectric bonds and metal-metal bonds, the metal-metal bonds include first bond-pads in the first IC die and second bond-pads in the second IC dies, the first IC die comprises a substrate attached to a metallization stack along a planar interface that is orthogonal to the first surface, the metallization stack comprises a plurality of layers of conductive traces in a dielectric material, and the first bond-pads comprise portions of the conductive traces exposed on the first surface.

公开(公告)号：US20230420376A1

公开(公告)日：2023-12-28

申请号：US18462600

申请日：2023-09-07

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Mohit Bhatia ,  Debendra Mallik

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L25/18

CPC classification number: H01L23/5385 ,  H01L2224/17181 ,  H01L25/0652 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L21/4857 ,  H01L21/4853 ,  H01L21/481 ,  H01L25/18 ,  H01L2224/1703 ,  H01L2224/73253 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L25/0655

Abstract: Disclosed herein are microelectronic structures including bridges, and related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate with first and second metal layers; a cavity in the substrate, where a portion of the first and second metal layers, are exposed with the portion of the first metal layer partially overlapping the portion of the second metal layer; and a bridge component in the cavity, having a first conductive contact at a first face and a second conductive contact at a second face opposing the first face, the second face towards a bottom surface of the cavity, the portion of the first metal layer is between the second face of the bridge component and the portion of the second metal layer, and the second conductive contact is electrically coupled to the portion of the second metal layer in the cavity.

公开(公告)号：US11791274B2

公开(公告)日：2023-10-17

申请号：US16902777

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Manish Dubey ,  Omkar G. Karhade ,  Nitin A. Deshpande ,  Jinhe Liu ,  Sairam Agraharam ,  Mohit Bhatia ,  Edvin Cetegen

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L23/5389 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/1703

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US20230089433A1

公开(公告)日：2023-03-23

申请号：US17482283

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Xiaoqian Li ,  Omkar G. Karhade ,  Nitin A. Deshpande ,  Srinivas V. Pietambaram

IPC: G02B6/42

Abstract: Microelectronic assemblies including photonic integrated circuits (PICs), related devices and methods, are disclosed herein. For example, in some embodiments, a photonic assembly may include a PIC in a first layer including an insulating material, wherein the PIC has an active side and an opposing backside, and wherein the PIC is embedded in the insulating material with the active side facing up; an optical component optically coupled to the active surface of the PIC and extending at least partially through the first layer; and an integrated circuit (IC) in a second layer, wherein the second layer is on the first layer, wherein the second layer includes the insulating material, wherein the IC is embedded in the insulating material in the second layer, and wherein the IC is electrically coupled to the active side of the PIC.

公开(公告)号：US20230080454A1

公开(公告)日：2023-03-16

申请号：US17473694

申请日：2021-09-13

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Brandon C. Marin ,  Debendra Mallik ,  Tarek A. Ibrahim ,  Jeremy Ecton ,  Omkar G. Karhade ,  Bharat Prasad Penmecha ,  Xiaoqian Li ,  Nitin A. Deshpande ,  Mitul Modi ,  Bai Nie

IPC: G02B6/12 ,  H01L23/48

Abstract: An optoelectronic assembly is disclosed, comprising a substrate having a core comprised of glass, and a photonic integrated circuit (PIC) and an electronic IC (EIC) coupled to a first side of the substrate. The core comprises a waveguide with a first endpoint proximate to the first side and a second endpoint exposed on a second side of the substrate orthogonal to the first side. The first endpoint of the waveguide is on a third side of the core parallel to the first side of the substrate. The substrate further comprises an optical via aligned with the first endpoint, and the optical via extends between the first side and the third side. In various embodiments, the waveguide is of any shape that can be inscribed by a laser between the first endpoint and the second endpoint.

公开(公告)号：US11417592B2

公开(公告)日：2022-08-16

申请号：US16328617

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nachiket R. Raravikar ,  Sandeep B. Sane

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a device disposed on first side of substrate and an array of conductive interconnect structures disposed on a second side of the first substrate. The conductive interconnect structures of the array may comprise a solder material, wherein the solder material comprises a low temperature alloying element concentration of less than about 5 percent. A second substrate is coupled to the array of conductive interconnect structures.

公开(公告)号：US20220199535A1

公开(公告)日：2022-06-23

申请号：US17126629

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.