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    INTERNAL ERROR CHECKING AND CORRECTION (ECC) WITH EXTRA SYSTEM BITS
    22.
    发明申请
    INTERNAL ERROR CHECKING AND CORRECTION (ECC) WITH EXTRA SYSTEM BITS 审中-公开

    公开(公告)号：US20180210787A1

    公开(公告)日：2018-07-26

    申请号：US15540798

    申请日：2017-05-02

    Applicant: Intel Corporation

    Inventor： Kuljit S. BAINS ,  Bill NALE ,  Rajat AGARWAL

    IPC: G06F11/10 ,  G11C29/52 ,  G11C11/4093

    Abstract: A memory subsystem includes a data bus to couple a memory controller to one or more memory devices. The memory controller and one or more memory devices transfer data for memory access operations. The data transfer includes the transfer of data bits and associated check bits over a transfer cycle burst. The memory devices include internal error checking and correction (ECC) separate from the system ECC managed by the memory controller. With a 2N transfer cycle for 2̂N data bits for a memory device, the memory devices can provide up to 2N memory locations for N+1 internal check bits, which can leave up to (2N minus (N+1)) extra bits to be used by the system for more robust ECC.

    MULTIPLEXED RANKS (MR) WITH PSEUDO BURST LENGTH 32 (BL32)
    24.
    发明申请
    MULTIPLEXED RANKS (MR) WITH PSEUDO BURST LENGTH 32 (BL32) 有权

    公开(公告)号：US20230071117A1

    公开(公告)日：2023-03-09

    申请号：US17987687

    申请日：2022-11-15

    Applicant: Intel Corporation

    Inventor： Hussein ALAMEER ,  Bill NALE ,  George VERGIS ,  Rajat AGARWAL

    IPC: G06F3/06

    Abstract: A memory module has a registering clock driver (RCD) that issues two column address strobe (CAS) commands with a single memory access command to exchange a double amount of data per dynamic random access memory (DRAM) device per memory access command. With double the amount of data per DRAM device, the memory module can provide double the pseudo channels as compared to a memory module where a single CAS command is issued per access command. The RCD can time division multiplex separate first commands for a first group of the DRAM devices from second commands for a second group of the DRAM devices on the command/address (CA) bus.

    FAST MEMORY ECC ERROR CORRECTION
    27.
    发明申请
    FAST MEMORY ECC ERROR CORRECTION 有权

    公开(公告)号：US20220107866A1

    公开(公告)日：2022-04-07

    申请号：US17550859

    申请日：2021-12-14

    Applicant: Intel Corporation

    Inventor： Jing LING ,  Wei P. CHEN ,  Rajat AGARWAL

    IPC: G06F11/10 ,  G06F11/14

    Abstract: A memory controller having an error checking and correction (ECC) circuitry can detect an error in data being read from memory and correct that error with a retry flow. The read data is stored in a read data buffer at the memory controller when the read data is received from memory. Once the ECC circuitry detects an error in the read data, the retry flow enables access to that data from the read data buffer instead of reading the data from memory for the second time. Access to the data from the read data buffer reduces the overall time needed for the correction flow compared to a retry flow that rereads the data from memory.

    TWO-LEVEL MAIN MEMORY HIERARCHY MANAGEMENT
    28.
    发明申请
    TWO-LEVEL MAIN MEMORY HIERARCHY MANAGEMENT 有权

    公开(公告)号：US20210216452A1

    公开(公告)日：2021-07-15

    申请号：US17214818

    申请日：2021-03-27

    Applicant: Intel Corporation

    Inventor： Sai Prashanth MURALIDHARA ,  Alaa R. ALAMELDEEN ,  Rajat AGARWAL ,  Wei P. CHEN ,  Vivek KOZHIKKOTTU

    IPC: G06F12/0802 ,  G06F3/06

    Abstract: A two-level main memory in which both volatile memory and persistent memory are exposed to the operating system in a flat manner and data movement and management is performed in cache line granularity is provided. The operating system can allocate pages in the two-level main memory randomly across the first level main memory and the second level main memory in a memory-type agnostic manner, or, in a more intelligent manner by allocating predicted hot pages in first level main memory and predicted cold pages in second level main memory. The cache line granularity movement is performed in a “swap” manner, that is, a hot cache line in the second level main memory is swapped with a cold cache line in first level main memory because data is stored in either first level main memory or second level main memory not in both first level main memory and second level main memory.

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