公开(公告)号：US20240213331A1

公开(公告)日：2024-06-27

申请号：US18088542

申请日：2022-12-24

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Pratik KOIRALA ,  Wesley HARRISON ,  Marko RADOSAVLJEVIC

IPC: H01L29/20 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/2003 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7838

Abstract: Gallium nitride (GaN) layer on substrate carburization for integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate including silicon. A layer comprising silicon and carbon is above the substrate. A layer comprising gallium and nitrogen is on the layer comprising silicon and carbon.

公开(公告)号：US20190393332A1

公开(公告)日：2019-12-26

申请号：US16016411

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA ,  Paul FISCHER ,  Walid HAFEZ

IPC: H01L29/778 ,  H01L29/08 ,  H01L29/20 ,  H01L29/205 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, an epitaxial layer on the substrate, a semiconductor interlayer on top of the epitaxial layer, a gate conductor above the semiconductor interlayer, a gate insulator on the bottom and sides of the gate conductor and contacting the top surface of the semiconductor interlayer, a source region extending into the epitaxial layer, and a drain region extending into the epitaxial layer. The semiconductor device also includes a first polarization layer on the semiconductor interlayer between the source region and the gate conductor and a second polarization layer on the semiconductor interlayer between the drain region and the gate conductor.

公开(公告)号：US20190393210A1

公开(公告)日：2019-12-26

申请号：US16016396

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Paul FISCHER ,  Walid HAFEZ

IPC: H01L27/02 ,  H01L29/20 ,  H01L29/06 ,  H01L29/872 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L21/265

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, an epitaxial layer above the substrate, a Schottky barrier material on the epitaxial layer, a Schottky metal contact extending into the Schottky barrier material, a fin structure that extends in a first direction, a first angled implant in a first side of the fin structure that has an orientation that is orthogonal to the first direction, and a second angled implant in a second side of the fin structure that has an orientation that is orthogonal to the first direction. The second side is opposite to the first side. A first cathode region and a second cathode region are coupled by parts of the first angled implant and the second angled implant that extend in the first direction.

公开(公告)号：US20190393041A1

公开(公告)日：2019-12-26

申请号：US16013860

申请日：2018-06-20

Applicant: Intel Corporation

Inventor： Marko RADOSAVLJEVIC ,  Han Wui THEN ,  Sansaptak DASGUPTA ,  Paul FISCHER ,  Walid HAFEZ

IPC: H01L21/28 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L29/778 ,  H01L29/66

Abstract: A transistor gate is disclosed. The transistor gate includes a first part above a substrate that has a first width and a second part above the first part that is centered with respect to the first part and that has a second width that is greater than the first width. The first part and the second part form a single monolithic T-gate structure.

公开(公告)号：US20190207003A1

公开(公告)日：2019-07-04

申请号：US16326857

申请日：2016-09-29

Applicant: INTEL CORPORATION

Inventor： Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA ,  Han Wui THEN

IPC: H01L29/20 ,  H01L29/08 ,  H01L29/205 ,  H01L29/66

CPC classification number: H01L29/2003 ,  H01L29/0847 ,  H01L29/0895 ,  H01L29/205 ,  H01L29/66522 ,  H01L29/66545

Abstract: Methods and apparatus for semiconductor manufacture are disclosed. An example apparatus includes a Gallium Nitride (GaN) substrate; a p-type GaN region positioned on the GaN substrate; a p-type Indium Nitride (InN) region positioned on the GaN substrate and sharing an interface with the p-type GaN region; and a n-type Indium Gallium Nitride (InGaN) region positioned on the GaN substrate and sharing an interface with the p-type InN region.

公开(公告)号：US20190148533A1

公开(公告)日：2019-05-16

申请号：US16242949

申请日：2019-01-08

Applicant: Intel Corporation

Inventor： Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA ,  Sanaz K. GARDNER ,  Seung Hoon SUNG ,  Han Wui THEN ,  Robert S. CHAU

IPC: H01L29/778 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/205 ,  H01L21/8258

CPC classification number: H01L29/7786 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/02647 ,  H01L21/823431 ,  H01L21/8252 ,  H01L21/8258 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/0891 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462

Abstract: Semiconductor devices including an elevated or raised doped crystalline structure extending from a device layer are described. In embodiments, III-N transistors include raised crystalline n+ doped source/drain structures on either side of a gate stack. In embodiments, an amorphous material is employed to limit growth of polycrystalline source/drain material, allowing a high quality source/drain doped crystal to grow from an undamaged region and laterally expand to form a low resistance interface with a two-degree electron gas (2DEG) formed within the device layer. In some embodiments, regions of damaged GaN that may spawn competitive polycrystalline overgrowths are covered with the amorphous material prior to commencing raised source/drain growth.

公开(公告)号：US20180350985A1

公开(公告)日：2018-12-06

申请号：US15779070

申请日：2015-12-24

Applicant: INTEL CORPORATION

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/16 ,  H01L29/20 ,  H01L29/267 ,  H01L27/092 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238

CPC classification number: H01L29/7848 ,  H01L21/0254 ,  H01L21/02645 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/267 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: Transistors including doped heteroepitaxial III-N source/drain crystals. In embodiments, transistors including a group IV or group III-V channel crystal employ n+ doped III-N source/drain structures on either side of a gate stack. Lateral tensile strain of the channel crystal may result from lattice mismatch between the channel crystal and the III-N source/drain crystals. In embodiments, an amorphous material is employed to limit growth of III-N material to only a single channel crystal facet, allowing a high quality monocrystalline source/drain to form that is capable of sustaining significant stress. In some embodiments, an n+ III-N source/drain crystal is grown on a (110) or (111) surface of a silicon channel crystal fabricated into a fin structure to form a tensile strained NMOS finFET.

公开(公告)号：US20180315659A1

公开(公告)日：2018-11-01

申请号：US15528031

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Sanaz K. GARDNER ,  Seung Hoon SUNG ,  Robert S. CHAU ,  Ravi PILLARISETTY

IPC: H01L21/8252 ,  H01L33/00 ,  H01L33/08 ,  H01L33/12 ,  H01L33/24 ,  H01L33/32

CPC classification number: H01L21/8252 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L33/007 ,  H01L33/08 ,  H01L33/10 ,  H01L33/12 ,  H01L33/24 ,  H01L33/32 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure are directed toward an integrated circuit (IC) die. In embodiments, an IC die may include a semiconductor substrate and a buffer layer disposed over the semiconductor substrate. The buffer layer may have a plurality of openings formed therein. In embodiments, the IC die may further include a plurality of group III-Nitride structures. Individual group III-Nitride structures of the plurality of group III-Nitride structures may include a lower portion disposed in a respective opening of the plurality of openings and an upper portion disposed over the respective opening. In embodiments, the upper portion may include a base extending radially from sidewalls of the respective opening over a surface of the buffer layer to form a perimeter around the respective opening. Other embodiments may be described and/or claimed.

公开(公告)号：US20170352532A1

公开(公告)日：2017-12-07

申请号：US15527287

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Robert S. CHAU ,  Sanaz K. GARDNER ,  Seung Hoon SUNG

IPC: H01L21/02 ,  H01L21/027 ,  H01L21/8258 ,  H01L27/06 ,  H01L29/06 ,  H01L29/66 ,  H01L29/32 ,  H01L29/225 ,  H01L29/205 ,  H01L29/20 ,  H01L29/08 ,  H01L29/778 ,  H01L29/22 ,  H01L27/092 ,  H01L23/00

CPC classification number: H01L21/0265 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02551 ,  H01L21/02554 ,  H01L21/02557 ,  H01L21/0256 ,  H01L21/02562 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/02647 ,  H01L21/0274 ,  H01L21/8258 ,  H01L23/48 ,  H01L24/16 ,  H01L25/065 ,  H01L27/0605 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/2203 ,  H01L29/225 ,  H01L29/267 ,  H01L29/32 ,  H01L29/66462 ,  H01L29/66969 ,  H01L29/7786 ,  H01L2224/16227 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) die. In embodiments, an IC die may include a semiconductor substrate, a group III-Nitride or II-VI wurtzite layer disposed over the semiconductor substrate, and a plurality of buffer structures at least partially embedded in the group III-Nitride or II-VI wurtzite layer. In some embodiments, each of the plurality of buffer structures may include a central member disposed over the semiconductor substrate, a lower lateral member disposed over the semiconductor substrate and extending laterally away from the central member, and an upper lateral member disposed over the central member and extending laterally from the central member in an opposite direction from the lower lateral member. The plurality of buffer structures may be positioned in a staggered arrangement to terminate defects of the group III-Nitride or II-VI wurtzite layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20170323946A1

公开(公告)日：2017-11-09

申请号：US15656480

申请日：2017-07-21

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Sanaz GARDNER ,  Seung Hoon SUNG ,  Robert S. Chau

IPC: H01L29/20 ,  H01L21/02 ,  H01L29/78 ,  H01L29/778 ,  H01L29/66 ,  H01L29/423 ,  H01L29/201 ,  H01L29/06 ,  H01L27/12 ,  H01L21/84 ,  H01L21/285 ,  H01L21/283 ,  H01L29/80

CPC classification number: H01L29/2003 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0228 ,  H01L21/0254 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/201 ,  H01L29/42356 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/802

Abstract: A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.