公开(公告)号：US10127184B2

公开(公告)日：2018-11-13

申请号：US15277893

申请日：2016-09-27

Applicant: INTEL CORPORATION

Inventor： Eng Hun Ooi ,  Su Wei Lim

IPC: H03M13/11 ,  G06F13/42 ,  G06F11/10 ,  G06F11/34 ,  G06F11/30

Abstract: An apparatus is described. The apparatus includes a point-to-point link interface circuit. The point-to-point link interface circuit is to support communication with a level of a multi-level system memory. The point-to-point link interface circuit includes a circuit to interlace payload data with cyclic redundancy check (CRC) values, where, different data segments of the payload are each appended with its own respective CRC value.

公开(公告)号：US20170235701A1

公开(公告)日：2017-08-17

申请号：US15503097

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： Akshay Pethe ,  Mahesh Wagh ,  David Harriman ,  Su Wei Lim ,  Debendra Das Sharma ,  Daniel Froelich ,  Venkatraman Iyer ,  James Jaussi ,  Zuoguo Wu

IPC: G06F13/42 ,  G06F13/38

CPC classification number: G06F13/4286 ,  G06F13/385 ,  G06F13/4027 ,  G06F2213/0042 ,  G06F2213/4002

Abstract: Techniques for embedded high speed serial interface methods are described herein. The techniques include an apparatus for sideband signaling including a first serial sideband link module and a second serial sideband link module. The first serial sideband link module is to propagate packets from an upstream port to a downstream port via a first signaling lane, and the second serial sideband link module is to propagate packets from the downstream port to the upstream port via a second signaling lane.

公开(公告)号：US20170024343A1

公开(公告)日：2017-01-26

申请号：US15218727

申请日：2016-07-25

Applicant: Intel Corporation

Inventor： Mikal C. Hunsaker ,  Su Wei Lim ,  Ricardo E. James

IPC: G06F13/364 ,  G11C29/52 ,  G06F13/42 ,  G06F11/10 ,  G06F11/07

CPC classification number: G06F13/364 ,  G06F1/06 ,  G06F1/24 ,  G06F11/0727 ,  G06F11/0745 ,  G06F11/1004 ,  G06F11/1072 ,  G06F11/221 ,  G06F11/2289 ,  G06F11/3027 ,  G06F13/00 ,  G06F13/122 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/423 ,  G06F13/4234 ,  G06F13/4282 ,  G06F13/4291 ,  G11C29/52

Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.

Abstract translation: 具有组件间通信能力的分量设备和具有这种组件设备的系统在此被公开。 在实施例中，这样的组件可以包括多个控制引脚，包括时钟引脚，多个数据引脚和逻辑单元。 逻辑单元可以被配置为通过时钟引脚从另一个组件接收时钟信号，以通过所选择的一个控制和数据引脚向另一个组件提供警报信号，以启动与另一个组件的交易，以便接收 通过数据引脚响应来自其他组件的警报信号，以确定事务的性质的状态请求，并且通过数据引脚向另一个组件响应状态请求来提供表示事务性质的状态。 提供警报信号，接收状态请求和提供状态可以参考时钟信号。 可以公开或要求保护其他实施例。

公开(公告)号：US09513662B2

公开(公告)日：2016-12-06

申请号：US13734612

申请日：2013-01-04

Applicant: Intel Corporation

Inventor： Jennifer Chin ,  Su Wei Lim ,  Poh Thiam Teoh ,  Ting Lok Song ,  Sun Zheng E ,  Say Cheong Gan ,  Sujea Lim ,  Ming Yi Lim

IPC: G06F1/00 ,  G06F1/16 ,  G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/1626 ,  G06F1/3206 ,  G06F1/3218 ,  G06F1/3243 ,  G06F13/4282 ,  G06F2213/0026 ,  Y02D10/151 ,  Y02D10/152

Abstract: Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device.

Abstract translation: 本文描述的特定实施例可以提供一种用于管理至少一个处理器的功率的方法，该处理器包括评估与电子设备相关联的多个端口; 确定与所述端口中的至少一个相关联的特定引脚没有接收到信号; 禁用与所述电子设备相关联的静噪功能; 以及与电子设备的物理层（PHY）相关联的门控功率。

公开(公告)号：US20160283429A1

公开(公告)日：2016-09-29

申请号：US14669975

申请日：2015-03-26

Applicant: Intel Corporation

Inventor： Mahesh Wagh ,  Zuoguo Wu ,  Venkatraman Iyer ,  Gerald S. Pasdast ,  Mark S. Birrittella ,  Ishwar Agarwal ,  Lip Khoon Teh ,  Su Wei Lim ,  Anoop Kumar Upadhyay

IPC: G06F13/40 ,  G06F13/36 ,  G01R31/317

CPC classification number: G06F13/4022 ,  G06F13/36 ,  G06F13/4068

Abstract: A system-on-a-chip, such as a logical PHY, may be divided into hard IP blocks with fixed routing, and soft IP blocks with flexible routing. Each hard IP block may provide a fixed number of lanes. Using p hard IP blocks, where each block provides n data lanes, h=n*p total hard IP data lanes are provided. Where the system design calls for k total data lanes, it is possible that k≠h, so that [k/n] hard IP blocks provide h=n*p available hard IP data lanes. In that case, h−k lanes may be disabled. In cases where lane reversals occur, such as between hard IP and soft IP, bowtie routing may be avoided by the use of a multiplexer-like programmable switch within the soft IP.

Abstract translation: 诸如逻辑PHY的片上系统可以被划分为具有固定路由的硬IP块和具有灵活路由的软IP块。 每个硬IP块可以提供固定数量的车道。 使用p硬IP块，其中每个块提供n个数据通道，h = n * p提供总硬IP数据通道。 在系统设计要求k个总数据通道的情况下，k≠h可以使得[k / n]硬IP块提供h = n * p可用的硬IP数据通道。 在这种情况下，h-k通道可能被禁用。 在发生通道反转的情况下，例如在硬IP和软IP之间，可以通过使用软IP内的多路复用器可编程开关来避免路由路由。

公开(公告)号：US09152596B2

公开(公告)日：2015-10-06

申请号：US13718067

申请日：2012-12-18

Applicant: Intel Corporation

Inventor： Mahesh Wagh ,  Su Wei Lim

IPC: H04J3/16 ,  G06F13/40 ,  H04L12/24 ,  H04L12/917 ,  H04L12/911

CPC classification number: G06F13/4027 ,  G06F13/4282 ,  G06N99/005 ,  H04L41/0896 ,  H04L47/76 ,  H04L47/824

Abstract: In one embodiment, a device having a link training state machine including a reconfiguration logic to perform a dynamic link reconfiguration of a physical link coupled between the device and a second device during a run-time in which the physical link does not enter a link down state, including transmission of a plurality of bandwidth change requests to the second device, each of the plurality of bandwidth change requests to request a bandwidth change from a first bandwidth to a second bandwidth. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，具有链路训练状态机的设备包括重配置逻辑，以在物理链路不进入链路的运行时间内对耦合在设备和第二设备之间的物理链路进行动态链路重新配置 状态，包括向所述第二设备发送多个带宽改变请求，所述多个带宽改变请求中的每一个请求从第一带宽到第二带宽的带宽改变。 描述和要求保护其他实施例。

公开(公告)号：US20150212959A1

公开(公告)日：2015-07-30

申请号：US14668013

申请日：2015-03-25

Applicant: Intel Corporation

Inventor： Mikal Hunsaker ,  Su Wei Lim ,  Ricardo E. James

IPC: G06F13/364 ,  G06F13/16 ,  G06F11/30 ,  G06F13/42

CPC classification number: G06F13/364 ,  G06F1/06 ,  G06F1/24 ,  G06F11/0727 ,  G06F11/0745 ,  G06F11/1004 ,  G06F11/1072 ,  G06F11/221 ,  G06F11/2289 ,  G06F11/3027 ,  G06F13/00 ,  G06F13/122 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/423 ,  G06F13/4234 ,  G06F13/4282 ,  G06F13/4291 ,  G11C29/52

Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.

公开(公告)号：US20220156211A1

公开(公告)日：2022-05-19

申请号：US17559427

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Eng Hun Ooi ,  Su Wei Lim ,  Vaibhav Khamkar

IPC: G06F13/40 ,  G06F13/42 ,  G06F15/78 ,  G06F9/455

Abstract: Systems or methods of the present disclosure may provide a peripheral component interconnect express (PCIe) device that comprises a programmable fabric. The programmable fabric comprises multiple PCIe physical functions. The programmable fabric also includes switch circuitry having one or more embedded endpoints that dynamically hides or exposes one or more of the multiple PCIe physical functions from a bare metal mode host server without using a reset.

公开(公告)号：US11163717B2

公开(公告)日：2021-11-02

申请号：US16921498

申请日：2020-07-06

Applicant: Intel Corporation

Inventor： Michelle Jen ,  Dan Froelich ,  Debendra Das Sharma ,  Bruce Tennant ,  Quinn Devine ,  Su Wei Lim

IPC: G06F13/42 ,  G06F13/38 ,  G06F13/40 ,  H04L29/06 ,  H04L29/08

Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.

公开(公告)号：US20210056067A1

公开(公告)日：2021-02-25

申请号：US16921498

申请日：2020-07-06

Applicant: Intel Corporation

Inventor： Michelle Jen ,  Dan Froelich ,  Debendra Das Sharma ,  Bruce Tennant ,  Quinn Devine ,  Su Wei Lim

IPC: G06F13/42 ,  G06F13/38 ,  G06F13/40

Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.