公开(公告)号：US20150041912A1

公开(公告)日：2015-02-12

申请号：US14135381

申请日：2013-12-19

Applicant: Intermolecular, Inc.

Inventor： Khaled Ahmed ,  Frank Greer

IPC: H01L21/28 ,  H01L27/092

CPC classification number: H01L21/28158 ,  H01L21/0215 ,  H01L21/0228 ,  H01L21/28255 ,  H01L21/28264 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/16 ,  H01L29/20 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

Abstract: Provided are field effect transistor (FET) assemblies and methods of forming thereof. An FET assembly may include a dielectric layer formed from tantalum silicon oxide and having the atomic ratio of silicon to tantalum and silicon (Si/(Ta+Si)) of less than 5% to provide a low trap density. The dielectric layer may be disposed over an interface layer, which is disposed over a channel region. The same type of the dielectric layer may be used a common gate dielectric of an nMOSFET (e.g., III-V materials) and a pMOSFET (e.g., germanium). The channel region may include one of indium gallium arsenide, indium phosphate, or germanium. The interface layer may include silicon oxide to provide a higher energy barrier. The dielectric layer may be formed using an atomic layer deposition technique by adsorbing both tantalum and silicon containing precursors on the deposition surface and then oxidizing both precursors in the same operation.

Abstract translation: 提供场效应晶体管（FET）组件及其形成方法。 FET组件可以包括由钽氧化硅形成并且具有小于5％的硅与钽和硅（Si /（Ta + Si））的原子比的介电层以提供低陷阱密度。 电介质层可以设置在界面层上，该界面层设置在沟道区域上。 可以使用相同类型的电介质层的nMOSFET（例如，III-V材料）和pMOSFET（例如，锗）的公共栅极电介质。 沟道区可以包括砷化铟镓，磷酸铟或锗中的一种。 界面层可以包括氧化硅以提供更高的能量势垒。 可以使用原子层沉积技术，通过在沉积表面上吸附含有钽和硅的两种前体，然后在相同的操作中氧化两种前体来形成电介质层。

公开(公告)号：US20140159120A1

公开(公告)日：2014-06-12

申请号：US13706619

申请日：2012-12-06

Applicant: INTERMOLECULAR, INC.

Inventor： Khaled Ahmed

IPC: H01L21/225 ,  H01L29/36

CPC classification number: H01L21/2258 ,  H01L21/2254 ,  H01L21/268 ,  H01L29/66803

Abstract: Methods for doping a three-dimensional semiconductor structure are disclosed. A conformal coating is formed on the three-dimensional semiconductor structure by Atomic Layer Deposition, and subsequent annealing causes dopant atoms to migrate into the three-dimensional semiconductor structure. Any residual conformal coating is then removed by etching. The semiconductor can be a type IV semiconductor such as Si, SiC, SiGe, or Ge, for which Sb and Te are suitable dopants. Sb and Te can be provided from a Ge2Sb2Te5 conformal coating. The semiconductor can also be a type III-V semiconductor such as InGaAs, GaAs, InAs, or GaSb, for which Sn and S are suitable dopants. Sn and S can be provided from a SnS conformal coating. The dopant concentration can be adjusted by precise control over the number of monolayers deposited in a conformal coating layer deposited by ALD.

Abstract translation: 公开了掺杂三维半导体结构的方法。 通过原子层沉积在三维半导体结构上形成保形涂层，随后的退火使掺杂剂原子迁移到三维半导体结构中。 然后通过蚀刻去除任何残留的保形涂层。 半导体可以是诸如Si，SiC，SiGe或Ge的IV型半导体，其中Sb和Te是合适的掺杂剂。 Sb和Te可以由Ge2Sb2Te5保形涂层提供。 半导体也可以是诸如InGaAs，GaAs，InAs或GaSb的III-V族半导体，其中Sn和S是合适的掺杂剂。 Sn和S可以由SnS保形涂层提供。 可以通过精确控制沉积在由ALD沉积的保形涂层中的单层数量来调节掺杂剂浓度。

公开(公告)号：US20140065819A1

公开(公告)日：2014-03-06

申请号：US13672621

申请日：2012-11-08

Applicant: INTERMOLECULAR, INC.

Inventor： Khaled Ahmed ,  Tony P. Chiang

IPC: H01L21/3205

CPC classification number: H01L21/28556 ,  H01L21/2255 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/2855 ,  H01L29/665

Abstract: Methods for improving contact resistance, for example, to a semiconductor region such as a source or a drain region, are disclosed. The methods can include depositing a layer on a substrate, wherein the layer can include a first element to form a silicide with the substrate and a second element to lower a contact resistance between the silicide and the substrate. The second element can include a dopant, which can enhance trap assisted tunneling or lower the Schottky barrier height between the silicide layer and the substrate.

Abstract translation: 公开了用于提高接触电阻的方法，例如提供到诸如源极或漏极区域的半导体区域。 所述方法可以包括在衬底上沉积层，其中所述层可以包括与衬底形成硅化物的第一元件和第二元件以降低硅化物和衬底之间的接触电阻。 第二元素可以包括掺杂剂，其可以增强陷阱辅助隧穿或降低硅化物层和衬底之间的肖特基势垒高度。

公开(公告)号：US20140065799A1

公开(公告)日：2014-03-06

申请号：US14079467

申请日：2013-11-13

Applicant: Intermolecular, Inc.

Inventor： Khaled Ahmed

IPC: H01L21/30 ,  H01L21/285

CPC classification number: H01L21/3003 ,  H01L21/2236 ,  H01L21/2254 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/66803

Abstract: Methods for improving contact resistance, for example, to a semiconductor region such as a source or a drain region, are disclosed. The methods can include exposing the substrate to an activated hydrogen species to remove contaminant layers such as native oxide layers followed by exposing the substrate to plasma activated dopant species to passivate the surface. The methods can further include depositing a layer on a substrate, wherein the layer can include a first element to form a silicide with the substrate and a second element to lower a contact resistance between the silicide and the substrate. The second element can include a dopant, which can enhance trap assisted tunneling or lower the Schottky barrier height between the silicide layer and the substrate. The cleaning, passivation, and deposition steps are performed in-situ without breaking vacuum.

Abstract translation: 公开了用于提高接触电阻的方法，例如提供到诸如源极或漏极区域的半导体区域。 所述方法可以包括将底物暴露于活化的氢物质以除去诸如天然氧化物层之类的污染物层，然后将衬底暴露于等离子体活化的掺杂剂物质以钝化表面。 所述方法还可以包括在衬底上沉积层，其中该层可以包括与衬底形成硅化物的第一元件和第二元件以降低硅化物和衬底之间的接触电阻。 第二元素可以包括掺杂剂，其可以增强陷阱辅助隧穿或降低硅化物层和衬底之间的肖特基势垒高度。 清洁，钝化和沉积步骤在原位进行而不破坏真空。

公开(公告)号：US20160181430A1

公开(公告)日：2016-06-23

申请号：US14575687

申请日：2014-12-18

Applicant: Intermolecular Inc.

Inventor： Khaled Ahmed

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/423 ,  H01L23/532 ,  H01L21/441 ,  H01L29/45 ,  H01L21/768 ,  H01L27/12 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7869 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/02667 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L27/124 ,  H01L29/45 ,  H01L29/66969 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments described herein provide indium-gallium-zinc oxide (IGZO) devices, such as IGZO thin-film transistors (TFTs), and methods for forming such devices. A substrate is provided. A gate electrode is formed above the substrate. A gate dielectric layer is formed above the gate electrode. An IGZO channel layer is formed above the gate dielectric layer. The IGZO channel layer includes crystalline IGZO. An electrode is formed above the IGZO channel layer. The electrode comprises titanium, aluminum, and nitrogen.

Abstract translation: 本文所述的实施例提供诸如IGZO薄膜晶体管（TFT）的铟镓锌氧化物（IGZO）器件，以及用于形成这种器件的方法。 提供基板。 在基板上方形成栅电极。 栅极电介质层形成在栅电极上。 在栅介电层上形成IGZO沟道层。 IGZO沟道层包括晶体IGZO。 在IGZO沟道层上方形成电极。 电极包括钛，铝和氮。

公开(公告)号：US09136355B2

公开(公告)日：2015-09-15

申请号：US14095834

申请日：2013-12-03

Applicant: Intermolecular, Inc.

Inventor： Khaled Ahmed

IPC: H01L21/00 ,  H01L29/66

CPC classification number: H01L29/66765 ,  H01L29/458 ,  H01L29/78618 ,  H01L29/78669

Abstract: Embodiments described herein provide amorphous silicon thin-film transistors (a-Si TFTs) and methods for forming a-Si TFTs. A substrate is provided. A gate electrode is formed above the substrate. An a-Si channel layer is formed above the gate electrode. A contact layer is formed above the a-Si channel layer. The contact layer includes titanium, zinc, arsenic, or a combination thereof. A source electrode and a drain electrode are formed above the contact layer.

Abstract translation: 本文描述的实施例提供非晶硅薄膜晶体管（a-Si TFT）以及用于形成a-Si TFT的方法。 提供基板。 在基板上方形成栅电极。 在栅电极上方形成a-Si沟道层。 在a-Si沟道层上形成接触层。 接触层包括钛，锌，砷或其组合。 源电极和漏极形成在接触层上方。

公开(公告)号：US09082729B2

公开(公告)日：2015-07-14

申请号：US14085706

申请日：2013-11-20

Applicant: Intermolecular, Inc.

Inventor： Khaled Ahmed

IPC: H01L21/44 ,  H01L21/324 ,  H01L21/02 ,  H01L21/22 ,  H01L21/66

CPC classification number: H01L21/324 ,  B01J2219/0036 ,  B01J2219/00441 ,  B01J2219/00443 ,  B01J2219/00495 ,  B01J2219/00596 ,  B01J2219/00745 ,  B01J2219/00756 ,  C23C16/04 ,  C23C16/45563 ,  C23C16/45574 ,  C40B40/18 ,  C40B50/14 ,  C40B60/14 ,  H01L21/22 ,  H01L21/2252 ,  H01L21/2254 ,  H01L21/2258 ,  H01L22/14 ,  H01L22/20

Abstract: One or more small spot showerhead apparatus are used to provide dopant exposure and/or to deposit materials using CVD, PECVD, ALD, or PEALD on small spots in a site isolated, combinatorial manner. The small spot showerheads may be configured within a larger combinatorial showerhead to allow multi-layer film stacks to be deposited in a combinatorial manner. Anneal processes where the area of the process can be controlled such as laser annealing or site-isolated rapid thermal processing (RTP) can be used to vary the annealing conditions in a combinatorial manner.

Abstract translation: 使用一个或多个小型喷头装置以分离，组合的方式在小斑点上提供掺杂剂暴露和/或沉积材料，使用CVD，PECVD，ALD或PEALD。 小型喷头可配置在更大的组合喷淋头内，以允许以组合方式沉积多层胶片堆叠。 可以使用可以控制过程区域的退火方法，例如激光退火或位置分离快速热处理（RTP），以组合方式改变退火条件。

公开(公告)号：US09076651B1

公开(公告)日：2015-07-07

申请号：US14136271

申请日：2013-12-20

Applicant: Intermolecular, Inc.

Inventor： Khaled Ahmed ,  Frank Greer ,  Raj Jammy

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/02 ,  H01L29/40

CPC classification number: H01L21/02301 ,  C23C16/0227 ,  C23C16/56 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02307 ,  H01L21/02315 ,  H01L21/0234 ,  H01L21/0485 ,  H01L29/66068 ,  H01L29/78

Abstract: SiC substrates are cleaned and provided to a process chamber. In-situ plasma surface treatments are applied to further clean the surface of the substrate. A dielectric interface layer is deposited in-situ to passivate the surface. Metal layers having a low work function are deposited above the dielectric interface layer. The stack is annealed at about 500C in forming gas to form low resistivity ohmic contacts to the SiC substrate. SiC substrates are cleaned and provided to a process chamber. In-situ plasma surface treatments are applied to further clean the surface of the substrate. A silicon oxide dielectric interface layer is deposited in-situ to passivate the surface. Optional plasma surface treatments are applied to further improve the performance of the silicon oxide dielectric interface layer. An aluminum oxide gate dielectric layer is deposited above the silicon oxide dielectric interface layer.

Abstract translation: 将SiC衬底清洁并提供给处理室。 施加原位等离子体表面处理以进一步清洁基底的表面。 电介质界面层原位沉积以钝化表面。 具有低功函数的金属层沉积在电介质界面层的上方。 堆叠在大约500℃下在形成气体中退火以形成到SiC衬底的低电阻率欧姆接触。 将SiC衬底清洁并提供给处理室。 施加原位等离子体表面处理以进一步清洁基底的表面。 氧化硅介电界面层原位沉积以钝化表面。 施加可选的等离子体表面处理以进一步提高氧化硅介电界面层的性能。 在氧化硅介电界面层上沉积氧化铝栅极电介质层。

公开(公告)号：US09076641B2

公开(公告)日：2015-07-07

申请号：US14135431

申请日：2013-12-19

Applicant: Intermolecular, Inc.

Inventor： Khaled Ahmed

IPC: H01L21/283 ,  H01L21/02 ,  H01L29/66 ,  H01L21/285 ,  H01L27/146 ,  H01L29/41 ,  H01L21/3065 ,  H01L29/778 ,  H01L29/786 ,  H01L29/16

CPC classification number: H01L21/76864 ,  H01L21/02005 ,  H01L21/02104 ,  H01L21/02172 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02205 ,  H01L21/0228 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/3065 ,  H01L22/12 ,  H01L22/14 ,  H01L27/1462 ,  H01L27/14643 ,  H01L27/14698 ,  H01L29/1606 ,  H01L29/41 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/786

Abstract: Contacts for semiconductor devices and methods of making thereof are disclosed. A method comprises forming a first layer on a semiconductor, the first layer comprising one or more metals; forming a second layer on the first layer, the second layer comprising the one or more metals, nitrogen and oxygen; and heating the first and second layer such that oxygen migrates from the second layer into the first layer and the first layer comprises a sub-stoichiometric metal oxide after heating. Exemplary embodiments use transition metals such as Ti in the first layer. After heating there is a sub-stoichiometric oxide layer of about 2.5 nm thickness between a metal nitride conductor and the semiconductor. The specific contact resistivity is less than about 7×10−9 Ω·cm2.

Abstract translation: 公开了半导体器件的接触件及其制造方法。 一种方法包括在半导体上形成第一层，第一层包括一种或多种金属; 在所述第一层上形成第二层，所述第二层包含所述一种或多种金属，氮和氧; 以及加热所述第一层和所述第二层，使得氧从所述第二层迁移到所述第一层中，并且所述第一层在加热后包括亚化学计量的金属氧化物。 示例性实施例在第一层中使用诸如Ti之类的过渡金属。 在加热之后，在金属氮化物导体和半导体之间存在约2.5nm厚度的亚化学计量氧化层。 比接触电阻率小于约7×10-9＆OHgr·cm2。

公开(公告)号：US20150187956A1

公开(公告)日：2015-07-02

申请号：US14140777

申请日：2013-12-26

Applicant: Intermolecular Inc.

Inventor： Khaled Ahmed

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78609 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L2029/42388

Abstract: Embodiments described herein provide indium-gallium-zinc oxide (IGZO) devices, such as IGZO thin-film transistors (TFTs), and methods for forming such devices. A substrate is provided. A gate electrode is formed above the substrate. A gate dielectric layer is formed above the gate electrode. The gate dielectric layer includes titanium. An interface layer is formed above the gate dielectric layer. The interface layer includes silicon. An IGZO channel layer is formed above the interface layer. A source electrode and a drain electrode are formed above the IGZO channel layer.

Abstract translation: 本文所述的实施例提供诸如IGZO薄膜晶体管（TFT）的铟镓锌氧化物（IGZO）器件，以及用于形成这种器件的方法。 提供基板。 在基板上方形成栅电极。 栅极电介质层形成在栅电极上。 栅介电层包括钛。 界面层形成在栅介电层上。 界面层包括硅。 在界面层的上方形成IGZO沟道层。 源电极和漏极形成在IGZO沟道层上方。