公开(公告)号：US10410911B2

公开(公告)日：2019-09-10

申请号：US15833781

申请日：2017-12-06

Applicant: Infineon Technologies AG

Inventor： Carsten Schaeffer ,  Andreas Moser ,  Matthias Kuenle ,  Matteo Dainese ,  Roland Rupp ,  Hans-Joachim Schulze

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L29/739 ,  H01L21/8234 ,  H01L27/12 ,  H01L27/088

Abstract: A method of fabricating a semiconductor device includes forming a buried insulation region within a substrate by processing the substrate using etching and deposition processes. A semiconductor layer is formed over the buried insulation region at a first side of the substrate. Device regions are formed in the semiconductor layer. The substrate is thinned from a second side of the substrate to expose the buried insulation region. The buried insulation region is selectively removed to expose a bottom surface of the substrate. A conductive region is formed under the bottom surface of the substrate.

公开(公告)号：US20170271268A1

公开(公告)日：2017-09-21

申请号：US15458366

申请日：2017-03-14

Applicant: Infineon Technologies AG

Inventor： Frank Hille ,  Ravi Keshav Joshi ,  Michael Fugger ,  Oliver Humbel ,  Thomas Laska ,  Matthias Mueller ,  Roman Roth ,  Carsten Schaeffer ,  Hans-Joachim Schulze ,  Holger Schulze ,  Juergen Steinbrenner ,  Frank Umbach

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/53209 ,  H01L21/76846 ,  H01L21/76861 ,  H01L21/76898 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238

Abstract: According to an embodiment of a semiconductor device, the semiconductor devices includes a metal structure electrically connected to a semiconductor body and a metal adhesion and barrier structure between the metal structure and the semiconductor body. The metal adhesion and barrier structure includes a first layer having titanium and tungsten, and a second layer having titanium, tungsten, and nitrogen on the first layer having titanium and tungsten.

公开(公告)号：US09711621B2

公开(公告)日：2017-07-18

申请号：US14446741

申请日：2014-07-30

Applicant: Infineon Technologies AG

Inventor： Franz Hirler ,  Uwe Wahl ,  Thorsten Meyer ,  Michael Rüb ,  Armin Willmeroth ,  Markus Schmitt ,  Carolin Tolksdorf ,  Carsten Schaeffer

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/265 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/66689 ,  H01L21/26586 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66704 ,  H01L29/78 ,  H01L29/7825

Abstract: A trench transistor having a semiconductor body includes a source region, a body region, a drain region electrically connected to a drain contact, and a gate trench including a gate electrode which is isolated from the semiconductor body. The gate electrode is configured to control current flow between the source region and the drain region along at least a first side wall of the gate trench. The trench transistor further includes a doped semiconductor region having dopants introduced into the semiconductor body through an unmasked part of the walls of a trench.

公开(公告)号：US20160226477A1

公开(公告)日：2016-08-04

申请号：US14963509

申请日：2015-12-09

Applicant: Infineon Technologies AG

Inventor： Frank Pfirsch ,  Dorothea Werber ,  Anton Mauder ,  Carsten Schaeffer

IPC: H03K17/12 ,  H01L29/06 ,  H01L29/739

CPC classification number: H03K17/127 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/404 ,  H01L29/407 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7397 ,  H03K3/01 ,  H03K17/66

Abstract: According to an embodiment of a method, a semiconductor device is operated in a reverse biased unipolar mode before operating the semiconductor device in an off-state in a forward biased mode The semiconductor device includes at least one floating parasitic region disposed outside a cell region of the device.

Abstract translation: 根据方法的实施例，半导体器件在正向偏置模式中处于截止状态之前，以反向偏置单极模式工作。半导体器件包括至少一个浮置寄生区域，该浮置寄生区域设置在 装置。

公开(公告)号：US20150056788A1

公开(公告)日：2015-02-26

申请号：US14502882

申请日：2014-09-30

Applicant: Infineon Technologies AG

Inventor： Gerhard Schmidt ,  Josef-Georg Bauer ,  Carsten Schaeffer ,  Oliver Humbel ,  Angelika Koprowski ,  Sirinpa Monayakul

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/283 ,  H01L29/47

CPC classification number: H01L29/66143 ,  H01L21/02115 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02203 ,  H01L21/283 ,  H01L23/3171 ,  H01L23/3192 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/408 ,  H01L29/47 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8611 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor body with a first surface, a contact electrode arranged on the first surface, and a passivation layer on the first surface adjacent the contact electrode. The passivation layer includes a layer stack with an amorphous semi-insulating layer on the first surface, a first nitride layer on the amorphous semi-insulating layer, and a second nitride layer on the first nitride layer.

Abstract translation: 半导体器件包括具有第一表面的半导体本体，布置在第一表面上的接触电极以及与接触电极相邻的第一表面上的钝化层。 钝化层包括在第一表面上具有非晶半绝缘层的层叠层，非晶半绝缘层上的第一氮化物层和第一氮化物层上的第二氮化物层。

公开(公告)号：US20230343726A1

公开(公告)日：2023-10-26

申请号：US18215467

申请日：2023-06-28

Applicant: Infineon Technologies AG

Inventor： Angelika Koprowski ,  Oliver Humbel ,  Markus Kahn ,  Carsten Schaeffer

IPC: H01L23/00 ,  H01L29/40

CPC classification number: H01L23/564 ,  H01L29/402

Abstract: A high voltage semiconductor device includes a semiconductor substrate including an upper surface, a high voltage electrically conductive structure disposed on the semiconductor substrate, a first step topography at an edge of the high voltage electrically conductive structure, a varying lateral doping zone disposed within the semiconductor substrate, and a layer stack including an electrically insulating buffer layer, a SiC layer over the electrically insulating buffer layer, and a silicon nitride layer over the SiC layer or a nitrided surface region of the SiC layer, wherein the layer stack conforms to the first step topography and extends over the varying lateral doping zone.

公开(公告)号：US20210151391A1

公开(公告)日：2021-05-20

申请号：US17086979

申请日：2020-11-02

Applicant: Infineon Technologies AG

Inventor： Angelika Koprowski ,  Oliver Humbel ,  Markus Kahn ,  Carsten Schaeffer

IPC: H01L23/00 ,  H01L29/40

Abstract: A high voltage semiconductor device includes a high voltage electrically conductive structure and a step topography at or in the vicinity of the high voltage electrically conductive structure. A layer stack covers the step topography. The layer stack includes an electrically insulating buffer layer, a SiC layer over the electrically insulating buffer layer and a silicon nitride layer over the SiC layer or a nitrided surface region of the SiC layer.

公开(公告)号：US20200013722A1

公开(公告)日：2020-01-09

申请号：US16577316

申请日：2019-09-20

Applicant: Infineon Technologies AG

Inventor： Frank Hille ,  Ravi Keshav Joshi ,  Michael Fugger ,  Oliver Humbel ,  Thomas Laska ,  Matthias Müller ,  Roman Roth ,  Carsten Schaeffer ,  Hans-Joachim Schulze ,  Holger Schulze ,  Juergen Steinbrenner ,  Frank Umbach

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: According to an embodiment of a semiconductor device, the semiconductor devices includes a metal structure electrically connected to a silicon carbide semiconductor body and a metal adhesion and barrier structure between the metal structure and the silicon carbide semiconductor body. The metal adhesion and barrier structure includes a layer comprising titanium and tungsten.

公开(公告)号：US10002930B2

公开(公告)日：2018-06-19

申请号：US15365627

申请日：2016-11-30

Applicant: Infineon Technologies AG

Inventor： Roland Rupp ,  Jens Peter Konrath ,  Francisco Javier Santos Rodriguez ,  Carsten Schaeffer ,  Hans-Joachim Schulze ,  Werner Schustereder ,  Guenther Wellenzohn

IPC: H01L29/45 ,  H01L21/28 ,  H01L29/40 ,  H01L21/02 ,  H01L21/04 ,  H01L21/225 ,  H01L29/47 ,  H01L29/16 ,  H01L21/285 ,  H01L29/20

CPC classification number: H01L29/401 ,  H01L21/02697 ,  H01L21/043 ,  H01L21/046 ,  H01L21/0485 ,  H01L21/0495 ,  H01L21/2258 ,  H01L21/28575 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/45 ,  H01L29/452 ,  H01L29/47 ,  H01L29/861 ,  H01L29/872

Abstract: Disclosed is a method. The method includes forming a metal layer on a first surface of a semiconductor body; irradiating the metal layer with particles to move metal atoms from the metal layer into the semiconductor body and form a metal atom containing region in the semiconductor body; and annealing the semiconductor body. The annealing includes heating at least the metal atom containing region to a temperature of less than 500° C.

公开(公告)号：US20180166324A1

公开(公告)日：2018-06-14

申请号：US15833781

申请日：2017-12-06

Applicant: Infineon Technologies AG

Inventor： Carsten Schaeffer ,  Andreas Moser ,  Matthias Kuenle ,  Matteo Dainese ,  Roland Rupp ,  Hans-Joachim Schulze

IPC: H01L21/762 ,  H01L21/3065 ,  H01L29/08 ,  H01L29/10 ,  H01L21/265 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/76248 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/02647 ,  H01L21/02667 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/762 ,  H01L21/823481 ,  H01L21/823487 ,  H01L21/84 ,  H01L27/088 ,  H01L27/1207 ,  H01L29/06 ,  H01L29/0649 ,  H01L29/08 ,  H01L29/0804 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/10 ,  H01L29/1095 ,  H01L29/66 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7812 ,  H01L29/7813

Abstract: A method of fabricating a semiconductor device includes forming a buried insulation region within a substrate by processing the substrate using etching and deposition processes. A semiconductor layer is formed over the buried insulation region at a first side of the substrate. Device regions are formed in the semiconductor layer. The substrate is thinned from a second side of the substrate to expose the buried insulation region. The buried insulation region is selectively removed to expose a bottom surface of the substrate. A conductive region is formed under the bottom surface of the substrate.