公开(公告)号：US09337185B2

公开(公告)日：2016-05-10

申请号：US14561357

申请日：2014-12-05

Applicant: Infineon Technologies AG

Inventor： Frank Pfirsch ,  Dorothea Werber ,  Carsten Schaeffer

IPC: H01L21/70 ,  H01L21/8248 ,  H01L27/06 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/47 ,  H01L29/739 ,  H01L29/66 ,  H01L27/07

CPC classification number: H01L27/0635 ,  H01L27/0727 ,  H01L29/0615 ,  H01L29/0804 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/47 ,  H01L29/66348 ,  H01L29/7397

Abstract: A semiconductor device includes a first doping region extending from a main surface of a semiconductor substrate into the semiconductor substrate. Further, the semiconductor device includes a second doping region arranged adjacent to the first doping region. The first doping region includes at least one low doping dose portion extending from the main surface of the semiconductor substrate to the second doping region. A doping dose within the low doping dose portion of the first doping region is less than 3 times a breakdown charge. Additionally, the semiconductor device includes a first electrode structure in contact with the first doping region at the main surface of the semiconductor substrate. The work function of the first electrode structure at the main surface of the semiconductor substrate is larger than 4.9 eV or lower than 4.4 eV.

Abstract translation: 半导体器件包括从半导体衬底的主表面延伸到半导体衬底中的第一掺杂区域。 此外，半导体器件包括邻近第一掺杂区布置的第二掺杂区。 第一掺杂区域包括从半导体衬底的主表面延伸到第二掺杂区域的至少一个低掺杂剂量部分。 第一掺杂区域的低掺杂剂量部分内的掺杂剂量小于击穿电荷的3倍。 另外，半导体器件包括与半导体衬底的主表面处的第一掺杂区域接触的第一电极结构。 第一电极结构在半导体衬底的主表面上的功函数大于4.9eV或低于4.4eV。

公开(公告)号：US09136397B2

公开(公告)日：2015-09-15

申请号：US13906738

申请日：2013-05-31

Applicant: Infineon Technologies AG

Inventor： Jens Konrath ,  Hans-Joachim Schulze ,  Roland Rupp ,  Wolfgang Werner ,  Frank Pfirsch

IPC: H01L29/80 ,  H01L29/812 ,  H01L29/04 ,  H01L29/16 ,  H01L29/66 ,  H01L29/267 ,  H01L29/872

CPC classification number: H01L29/66909 ,  H01L29/04 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/47 ,  H01L29/66068 ,  H01L29/66431 ,  H01L29/66734 ,  H01L29/66787 ,  H01L29/66848 ,  H01L29/7827 ,  H01L29/8122 ,  H01L29/872

Abstract: A field-effect semiconductor device having a semiconductor body with a main surface is provided. The semiconductor body includes, in a vertical cross-section substantially orthogonal to the main surface, a drift layer of a first conductivity type, a semiconductor mesa of the first conductivity type adjoining the drift layer, substantially extending to the main surface and having two side walls, and two second semiconductor regions of a second conductivity type arranged next to the semiconductor mesa. Each of the two second semiconductor regions forms a pn-junction at least with the drift layer. A rectifying junction is formed at least at one of the two side walls of the mesa. Further, a method for producing a heterojunction semiconductor device is provided.

Abstract translation: 提供了具有主表面的半导体本体的场效应半导体器件。 半导体本体在基本上垂直于主表面的垂直横截面中包括第一导电类型的漂移层，邻接漂移层的第一导电类型的半导体台面，基本上延伸到主表面并具有两个侧面 壁，以及布置在半导体台面旁边的第二导电类型的两个第二半导体区域。 两个第二半导体区域中的每一个至少与漂移层形成pn结。 在台面的两个侧壁中的至少一个侧面上形成整流结。 此外，提供了一种异质结半导体器件的制造方法。

公开(公告)号：US20250006727A1

公开(公告)日：2025-01-02

申请号：US18753518

申请日：2024-06-25

Applicant: Infineon Technologies AG

Inventor： Frank Pfirsch ,  Roman Baburske

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/739 ,  H01L29/861 ,  H03K17/567

Abstract: An IGBT includes, in a single chip, an active region configured to conduct a forward load current between first and second load terminals at different sides of a semiconductor body. The active region is separated into at least first and second IGBT regions. At least 90% of the first IGBT region is configured to conduct, based on a first control signal, the forward load current. At least 90% of the second IGBT region is configured to conduct, based on a second control signal, the forward load current. A first MOS-channel-conductivity-to-area-ratio is determined by a total channel width in the first IGBT region divided by a total lateral area of first IGBT region. A second MOS-channel-conductivity-to-area-ratio is determined by a total channel width in the second IGBT region divided by a total lateral area of the second IGBT region. The second MOS-channel-conductivity-to-area-ratio amounts to less than 80% of the first MOS-channel-conductivity-to-area-ratio.

公开(公告)号：US20230275576A1

公开(公告)日：2023-08-31

申请号：US18115080

申请日：2023-02-28

Applicant: Infineon Technologies AG

Inventor： Roman BABURSKE ,  Frank Pfirsch ,  Jana HÃNSEL ,  Katja Waschneck

IPC: H03K17/0812 ,  H01L29/16 ,  H01L29/739 ,  H01L29/06

CPC classification number: H03K17/08128 ,  H01L29/1608 ,  H01L29/7397 ,  H01L29/0696

Abstract: A semiconductor switching module includes an insulated gate bipolar transistor and a unipolar switching device. The insulated gate bipolar transistor includes a first transistor cell and a supplemental cell, wherein the first transistor cell includes a first gate and a first source and wherein the supplemental cell includes a second gate and a supplemental electrode. The unipolar switching device is based on a wide bandgap material and includes a third gate and a third source. The third gate and the second gate are electrically connected with each other and are disconnected from the first gate. The first source, the supplemental cell and the third source are electrically connected with each other.

公开(公告)号：US20170133465A1

公开(公告)日：2017-05-11

申请号：US14936279

申请日：2015-11-09

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Frank Pfirsch ,  Hans-Joachim Schulze ,  Ingo Muri ,  Iris Moder ,  Johannes Baumgartl

IPC: H01L29/10 ,  H01L21/265 ,  H01L21/324 ,  H01L27/088 ,  H01L21/306 ,  H01L21/3205 ,  H01L29/78 ,  H01L29/66 ,  H01L21/304

CPC classification number: H01L29/1095 ,  H01L21/265 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/3205 ,  H01L21/324 ,  H01L27/088 ,  H01L29/0661 ,  H01L29/0834 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66136 ,  H01L29/66348 ,  H01L29/66477 ,  H01L29/7397 ,  H01L29/78

Abstract: In accordance with a method of forming a semiconductor device, an auxiliary structure is formed at a first surface of a silicon semiconductor body. A semiconductor layer is formed on the semiconductor body at the first surface. Semiconductor device elements are formed at the first surface. The semiconductor body is then removed from a second surface opposite to the first surface at least up to an edge of the auxiliary structure oriented to the second surface.

公开(公告)号：US09362349B2

公开(公告)日：2016-06-07

申请号：US13923436

申请日：2013-06-21

Applicant: Infineon Technologies AG

Inventor： Dorothea Werber ,  Frank Pfirsch ,  Hans-Joachim Schulze ,  Carsten Schaeffer ,  Volodymyr Komarnitskyy ,  Anton Mauder ,  Holger Schulze ,  Gerhard Miller

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/06 ,  H01L29/861 ,  H01L29/423 ,  H01L29/78 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/0615 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/423 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/8611

Abstract: A semiconductor device includes a cell region having at least one device cell, wherein the at least one device cell includes a first device region of a first conductivity type. The semiconductor device further includes a drift region of a second conductivity type adjoining the first device region of the at least one device cell, a doped region of the first conductivity type adjoining the drift region, and charge carrier lifetime reduction means configured to reduce a charge carrier lifetime in the doped region of the first conductivity type.

Abstract translation: 半导体器件包括具有至少一个器件单元的单元区域，其中至少一个器件单元包括第一导电类型的第一器件区域。 所述半导体器件还包括邻接所述至少一个器件单元的第一器件区域的第二导电类型的漂移区域，与所述漂移区域相邻的所述第一导电类型的掺杂区域以及被配置为减少电荷的电荷载流子寿命降低装置 在第一导电类型的掺杂区域中的载流子寿命。

公开(公告)号：US20150349097A1

公开(公告)日：2015-12-03

申请号：US14822267

申请日：2015-08-10

Applicant: Infineon Technologies AG

Inventor： Jens Konrath ,  Hans-Joachim Schulze ,  Roland Rupp ,  Wolfgang Werner ,  Frank Pfirsch

IPC: H01L29/66

CPC classification number: H01L29/66909 ,  H01L29/04 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/47 ,  H01L29/66068 ,  H01L29/66431 ,  H01L29/66734 ,  H01L29/66787 ,  H01L29/66848 ,  H01L29/7827 ,  H01L29/8122 ,  H01L29/872

Abstract: A method for forming a field-effect semiconductor device includes: providing a wafer having a main surface and a first semiconductor layer of a first conductivity type; forming at least two trenches from the main surface partly into the first semiconductor layer so that each of the at least two trenches includes, in a vertical cross-section substantially orthogonal to the main surface, a side wall and a bottom wall, and that a semiconductor mesa is formed between the side walls of the at least two trenches; forming at least two second semiconductor regions of a second conductivity type in the first semiconductor layer so that the bottom wall of each of the at least two trenches adjoins one of the at least two second semiconductor regions; and forming a rectifying junction at the side wall of at least one of the at least two trenches.

Abstract translation: 一种形成场效应半导体器件的方法包括：提供具有第一导电类型的主表面和第一半导体层的晶片; 从所述主表面形成至少两个沟槽部分地进入所述第一半导体层，使得所述至少两个沟槽中的每一个在基本上垂直于所述主表面的垂直横截面中包括侧壁和底壁，并且 在所述至少两个沟槽的侧壁之间形成半导体台面; 在所述第一半导体层中形成具有第二导电类型的至少两个第二半导体区域，使得所述至少两个沟槽中的每一个的底壁与所述至少两个第二半导体区域中的一个相邻; 以及在所述至少两个沟槽中的至少一个的侧壁的侧壁上形成整流结。

公开(公告)号：US09159819B2

公开(公告)日：2015-10-13

申请号：US14185117

申请日：2014-02-20

Applicant: Infineon Technologies AG

Inventor： Frank Pfirsch ,  Dorothea Werber

IPC: H01L29/06 ,  H01L29/739 ,  H01L29/40 ,  H01L29/66 ,  H01L21/266

CPC classification number: H01L29/7397 ,  H01L21/266 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/407 ,  H01L29/66348

Abstract: A semiconductor device includes a drift zone of a first conductivity type in a semiconductor body. Controllable cells are configured to form a conductive channel connected with the drift zone in a first state. First zones of the first conductivity type as well as second zones and a third zone of a complementary second conductivity type are between the drift zone and a rear side electrode, respectively. The first, second and third zones directly adjoin the rear side electrode. The third zone is larger and has a lower mean emitter efficiency than the second zones.

Abstract translation: 半导体器件包括半导体本体中的第一导电类型的漂移区。 可控电池被配置为在第一状态下形成与漂移区连接的导电通道。 第一导电类型的第一区以及第二区和互补第二导电类型的第三区分别位于漂移区和后侧电极之间。 第一，第二和第三区域直接毗邻后侧电极。 第三区域比第二区域更大，平均发射极效率较低。

公开(公告)号：US20140291809A1

公开(公告)日：2014-10-02

申请号：US14301995

申请日：2014-06-11

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Frank Pfirsch ,  Hans-Joerg Timme

IPC: H01L29/36 ,  H01L29/32 ,  H01L21/322 ,  H01L21/22 ,  H01L21/265

CPC classification number: H01L29/36 ,  H01L21/22 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/3225 ,  H01L29/32 ,  H03H9/02047 ,  H03H9/175

Abstract: The semiconductor substrate includes a high-ohmic semiconductor material with a conduction band edge and a valence band edge, separated by a bandgap, wherein the semiconductor material includes acceptor or donor impurity atoms or crystal defects, whose energy levels are located at least 120 meV from the conduction band edge, as well as from the valence band edge in the bandgap; and wherein the concentration of the impurity atoms or crystal defects is larger than 1×1012 cm−3.

Abstract translation: 半导体衬底包括具有导带边缘和价带边缘的高电阻半导体材料，带隙由带隙分开，其中半导体材料包括受体或施主杂质原子或晶体缺陷，其能级位于至少120meV 导带边缘，以及带隙中的价带边缘; 并且其中杂质原子或晶体缺陷的浓度大于1×10 12 cm -3。

公开(公告)号：US20240213343A1

公开(公告)日：2024-06-27

申请号：US18533872

申请日：2023-12-08

Applicant: Infineon Technologies AG

Inventor： Roland Dietmüller ,  Andreas Korzenietz ,  Bernd Bitnar ,  Wolfgang Wagner ,  Philip Christoph Brandt ,  Frank Hille ,  Volodymyr Komarnitskyy ,  Frank Pfirsch ,  Franz Josef Niedernostheide ,  Marc Probst

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/42364 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

Abstract: A power semiconductor device includes a first region in an active region of a semiconductor body and including first trenches each having a first trench electrode electrically connected to a gate terminal and a first trench insulator. A second region includes second trenches each having a second trench electrode electrically connected to the gate terminal and a second trench insulator. At least one of the following applies: a minimal thickness of each second trench insulator amounts to at least 120% of a corresponding minimal thickness of each first trench insulator; an average thickness of the second trench insulators amounts to at least 120% of an average thickness of the first trench insulators; a trench bottom thickness of each second trench insulator amounts to at least 120% of a corresponding trench bottom thickness of each first trench insulator; a minimal breakdown voltage of each second trench insulator amounts to at least 120% of a minimal breakdown voltage of each first trench insulator.