公开(公告)号：US20250105074A1

公开(公告)日：2025-03-27

申请号：US18977572

申请日：2024-12-11

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Wei Wei ,  Jose Fernando Waimin Almendares ,  Ryan Joseph Carrazzone ,  Kyle Jordan Arrington ,  Ziyin Lin ,  Dingying Xu ,  Hongxia Feng ,  Yiqun Bai ,  Hiroki Tanaka ,  Brandon Christian Marin ,  Jeremy Ecton ,  Benjamin Taylor Duong ,  Gang Duan ,  Srinivas Venkata Ramanuja Pietambaram ,  Rui Zhang ,  Mohit Gupta

IPC: H01L23/15 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498

Abstract: Glass cores including protruding through glass vias and related methods are disclosed herein. An example substrate disclosed herein includes a glass core including a surface and a copper through glass via (TGV) extending through the glass core, the TGV including a protrusion extending from the surface.

公开(公告)号：US12253722B2

公开(公告)日：2025-03-18

申请号：US17357788

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Hiroki Tanaka ,  Kristof Darmawikarta ,  Brandon Marin ,  Robert May ,  Sri Ranga Sai Boyapati

IPC: G02B6/42 ,  G02B5/30 ,  G02B27/12

Abstract: An optical package comprising an optical die that is electrically coupled to a package substrate, and an optical interconnect adjacent the optical die. The optical interconnect comprises a first polarizing filter adjacent to a first lens, a second polarizing filter adjacent to a second lens; and a film comprising a magnetic material between the first polarizing filter and the second polarizing filter. The second polarizing filter is rotated with respect to the first polarizing filter and the magnetic material is to rotate a polarization vector of light incoming to the optical interconnect. An optical fiber interface port is immediately adjacent to the first lens. The second lens is immediately adjacent to an optical interface of the optical die.

公开(公告)号：US20240329339A1

公开(公告)日：2024-10-03

申请号：US18191273

申请日：2023-03-28

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Changhua Liu ,  Hiroki Tanaka ,  Brandon C. Marin ,  Srinivas V. Pietambaram

IPC: G02B6/42 ,  G02B6/38

CPC classification number: G02B6/4228 ,  G02B6/3886 ,  G02B6/4239 ,  G02B6/4292

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a photonic integrated circuit (PIC) having a first surface having a channel and a first magnetic material; a fiber connector including a second surface with a second magnetic material; and a fiber physically coupled to the second surface of the fiber connector by an adhesive material; wherein the first surface of the PIC is coupled to the second surface of the fiber connector by the first and second magnetic materials with the fiber positioned in the channel.

公开(公告)号：US20240329333A1

公开(公告)日：2024-10-03

申请号：US18129690

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Robert May ,  Bai Nie ,  Changhua Liu ,  Hiroki Tanaka ,  Kristof Darmawikarta ,  Lilia May ,  Shriya Seshadri ,  Srinivas Pietambaram ,  Tarek Ibrahim

IPC: G02B6/42 ,  G02B6/13 ,  H01L25/065 ,  H01L25/16

CPC classification number: G02B6/4202 ,  G02B6/13 ,  H01L25/0655 ,  H01L25/167 ,  G02B2006/12038

Abstract: Multi-die packages including both photonic and electric integrated circuit (IC) die interconnected to each other through a routing structure built-up on a glass substrate. A glass preform comprising an optical waveguide may also be attached to the routing structure. A plurality of electrical IC (EIC) die may be arrayed over the routing structure along with a plurality of photonic IC (PIC). Each PIC may be coupled to an optical waveguide within the glass preform. Conductive vias may extend through the glass substrate and be further coupled with a host substrate. The host substrate may comprise glass and an optical waveguide embedded within the glass. A vertical coupler may be attached to the host substrate to optically couple the host substrate to the optical waveguide within the glass preform of the multi-die package. Many of the multi-die packages may be arrayed over a routing structure on the host substrate.

公开(公告)号：US20240128181A1

公开(公告)日：2024-04-18

申请号：US18047033

申请日：2022-10-17

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Srinivas V. Pietambaram ,  Hiroki Tanaka ,  Haobo Chen

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/14 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/145 ,  H01L23/49822 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L25/0655 ,  H01L24/32 ,  H01L2924/15311

Abstract: Embodiments of a microelectronic assembly that includes: a package substrate comprising a plurality of layers of organic dielectric material and conductive traces alternating with conductive vias in alternate layers of the organic dielectric material; and a plurality of integrated circuit dies coupled to a first side of the package substrate by interconnects, in which: the plurality of layers of the organic dielectric material comprises at least a first layer having a conductive via and a second layer having a conductive trace in contact with the conductive via, the second layer is not coplanar with the first layer, sidewalls of the conductive via are orthogonal to the conductive trace, and two opposing sidewalls of the conductive via separated by a width of the conductive via protrude from respectively proximate edges of the conductive trace by a protrusion that is at least ten times less than the width of the conductive via.

公开(公告)号：US20240111090A1

公开(公告)日：2024-04-04

申请号：US17957341

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Robert A. May ,  Tarek Ibrahim ,  Shriya Seshadri ,  Kristof Darmawikarta ,  Hiroki Tanaka ,  Changhua Liu ,  Bai Nie ,  Lilia May ,  Srinivas Pietambaram ,  Zhichao Zhang ,  Duye Ye ,  Yosuke Kanaoka ,  Robin McRee

IPC: G02B6/12 ,  G02B6/13

CPC classification number: G02B6/12004 ,  G02B6/13 ,  G02B2006/12171

Abstract: A device comprises a substrate and an IC die, which may be a photonic IC. The substrate comprises a first surface, a second surface opposite the first surface, an optical waveguide integral with the substrate, and a hole extending from the first surface to the second surface. The hole comprises a first sidewall. The optical waveguide is between the first surface and the second surface, parallel to the first surface, and comprises a first end which extends to the first sidewall. The IC die is within the hole and comprises a second sidewall and an optical port at the second sidewall. The second sidewall is proximate to the first sidewall and the first end of the optical waveguide is proximate to and aligned with the optical port. The substrate may include a recess to receive another device comprising a socket.

公开(公告)号：US20240071938A1

公开(公告)日：2024-02-29

申请号：US17900692

申请日：2022-08-31

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Hiroki Tanaka ,  Brandon Christian Marin ,  Srinivas V. Pietambaram ,  Suddhasattwa Nad

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/15 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/37001 ,  H01L2924/381

Abstract: A glass core with a cavity-less local interconnect component architecture for complex multi-die packages. The apparatus has the local interconnect component attached directly to a planar glass layer and surrounded by mold. One or more redistribution layers may be located above and below the apparatus.

公开(公告)号：US20240006298A1

公开(公告)日：2024-01-04

申请号：US17855040

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Steve Cho ,  Marcel Arlan Wall ,  Onur Ozkan ,  Ali Lehaf ,  Yi Yang ,  Jason Scott Steill ,  Gang Duan ,  Brandon C. Marin ,  Jeremy D. Ecton ,  Srinivas Venkata Ramanuja Pietambaram ,  Haifa Hariri ,  Bai Nie ,  Hiroki Tanaka ,  Kyle Mcelhinny ,  Jason Gamba ,  Venkata Rajesh Saranam ,  Kristof Darmawikarta ,  Haobo Chen

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49894 ,  H01L23/49816 ,  H01L21/4853 ,  H01L21/481 ,  H01L23/49838

Abstract: An electronic device may include an integrated circuit, for instance a semiconductor die. The electronic device may include a substrate having a first layer and a second layer. The first and second layers may include interconnects recessed below a surface of the substrate. The substrate may include a passivation layer directly coupled with portions of the interconnects. A solder resist material may at least partially cover portions of the passivation layer directly coupled with the first interconnect surface.

公开(公告)号：US20230420412A1

公开(公告)日：2023-12-28

申请号：US17847434

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Hiroki Tanaka ,  Kristof Kuwawi Darmawikarta ,  Robert Alan May ,  Sri Ranga Sai Boyapati ,  Srinivas V. Pietambaram

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/552

CPC classification number: H01L25/0652 ,  H01L23/5385 ,  H01L24/16 ,  H01L23/5384 ,  H01L23/3121 ,  H01L23/552 ,  H01L24/32 ,  H01L24/73 ,  H01L24/29 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/29294 ,  H01L2224/29293

Abstract: Embodiments of a microelectronic assembly comprise a microelectronic assembly, comprising: a package substrate; an interposer coupled to the package substrate, the interposer comprising a dielectric material, a conductive pillar) through the dielectric material and a conductive structure at least partially surrounding the conductive pillar, the conductive structure separated from the conductive pillar by the dielectric material; and an integrated circuit (IC) die coupled to the interposer on a side opposite to the package substrate. The conductive pillar conductively couples the IC die to the package substrate, and the conductive structure is coupled to a ground connection.

公开(公告)号：US20230350131A1

公开(公告)日：2023-11-02

申请号：US17733302

申请日：2022-04-29

Applicant: Intel Corporation

Inventor： Hiroki Tanaka ,  Bai Nie ,  Kristof Darmawikarta ,  Hari Mahalingam

IPC: G02B6/122 ,  G02B6/30

CPC classification number: G02B6/122 ,  G02B6/30 ,  G02B2006/12121

Abstract: Techniques for signal amplification for a photonic integrated circuit (PIC) die are disclosed. In the illustrative embodiment, an optical fiber is coupled to an input signal waveguide in a glass interposer, and an input signal waveguide of a PIC die is coupled to the input signal waveguide of the glass interposer. In order to compensate for any coupling losses, the input signal waveguide of the glass interposer is active, amplifying an input signal. Light in a pump waveguide near the input signal waveguide pumps ions in the input signal waveguide into a population inversion, allowing them to amplify the input signal.