公开(公告)号：US11782824B2

公开(公告)日：2023-10-10

申请号：US17667384

申请日：2022-02-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shuo-Nan Hung

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/0882 ,  G06F12/1045 ,  G06F13/16

CPC classification number: G06F12/0238 ,  G06F12/0882 ,  G06F12/1045 ,  G06F13/1673

Abstract: A data path for memory addressable using an addressing scheme based on a minimum addressable unit, such as a byte, having a size (e.g. 8) which is a power of 2, is configured for transferring data between the memory array and a data interface using a transfer storage unit having N bits (e.g. 12), where N is an integer that is not a power of 2. A page buffer and cache in the data path can be configured in unit arrays with N rows, and to transfer data in the transfer storage units from selected N cell columns.

公开(公告)号：US20220188238A1

公开(公告)日：2022-06-16

申请号：US17118239

申请日：2020-12-10

Applicant: MACRONIX International Co., Ltd.

Inventor： Chun-Lien Su ,  Chun-Hsiung Hung ,  Shuo-Nan Hung

IPC: G06F12/0882 ,  G06F12/0862 ,  G06F12/02 ,  G06F11/10

Abstract: A flash memory system and a flash memory thereof are provided. The flash memory device includes a NAND flash memory and a control circuit. The NAND flash memory chip includes a cache memory, a page buffer; and an NAND flash memory array. The NAND flash memory array includes a plurality of pages, wherein each page includes a plurality of sub-pages, each sub-page has a sub-page length. The cache memory is composed of a plurality of sub cache and each sub cache corresponds to different pages of the NAND flash memory array. The page buffer is composed of a plurality of sub-page buffers and each sub-page buffer corresponds to different pages of the NAND flash memory array. The control circuit is coupled to the host and the NAND flash memory, and performs an access operation in units of one sub-page.

公开(公告)号：US10977121B2

公开(公告)日：2021-04-13

申请号：US16533463

申请日：2019-08-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shuo-Nan Hung ,  Chun-Hsiung Hung

IPC: G06F11/10 ,  H03M13/15 ,  G11C11/4093 ,  G11C11/4094

Abstract: A memory device such as a page mode NAND flash is operated, using a first pipeline stage, to clear a page buffer to a second buffer level, and transfer a page to the page buffer; a second pipeline stage to clear the second buffer level to the third buffer level and transfer the page from the page buffer to the second buffer level; a third pipeline stage to move the page to the third buffer level and execute in an interleaved fashion a first ECC function over data in a first part of the page and output the first part of the page while performing an second ECC function, and to execute the first ECC function over data in a second part of the page in the third buffer level, and to output the second part while performing the second ECC function.

公开(公告)号：US10957384B1

公开(公告)日：2021-03-23

申请号：US16581562

申请日：2019-09-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ji-Yu Hung ,  Shuo-Nan Hung

IPC: G11C16/06 ,  G11C11/4094 ,  G11C29/00 ,  G11C29/42 ,  G11C11/4093

Abstract: A memory device such as a page mode NAND flash, including a page buffer with first and second-level buffer latches is operated using a first pipeline stage, to transfer a page to the first-level buffer latches; a second pipeline stage, to clear the second-level buffer latches to a third buffer level and transfer the page from the first-level buffer latches to the second-level buffer latches; and a third pipeline stage to move the page to the third buffer level and execute in an interleaved fashion a first ECC function over data in a first part of the page and output the first part of the page while performing a second ECC function, and to execute the first ECC function over data in a second part of the page in the third buffer level, and to output the second part while performing the second ECC function.

公开(公告)号：US10325662B2

公开(公告)日：2019-06-18

申请号：US15705001

申请日：2017-09-14

Applicant: MACRONIX International Co., Ltd.

Inventor： Shuo-Nan Hung ,  Shin-Jang Shen ,  Wei-Jen Chen

IPC: G11C11/34 ,  G11C16/06 ,  G11C16/14 ,  G11C16/04 ,  G11C16/08

Abstract: A circuit for adjusting a select gate voltage of a non-volatile memory is provided. The circuit includes a well, a select gate, and an adjustment unit. There is a capacitive coupling between the well and the select gate. The adjustment unit generates a driving voltage for the select gate based on a non-constant voltage.

公开(公告)号：US09152557B2

公开(公告)日：2015-10-06

申请号：US14265400

申请日：2014-04-30

Applicant: Macronix International Co., Ltd.

Inventor： Lung-Yi Kuo ,  Hsin-Yi Ho ,  Chun-Hsiung Hung ,  Shuo-Nan Hung ,  Han-Sung Chen

IPC: G06F3/06 ,  G06F12/02 ,  G11C16/10 ,  G11C11/56 ,  G06F11/00

CPC classification number: G06F12/0246 ,  G06F11/00 ,  G06F2212/7201 ,  G06F2212/7203 ,  G11C16/10 ,  G11C16/105 ,  G11C2211/5648

Abstract: A program method for a multi-level cell (MLC) flash memory is provided. The memory array includes a plurality of pages and a plurality of paired pages, which correspond to the respective pages. The program method includes the following steps. Firstly, a program address command is obtained. Next, whether the program address command corresponding to any one of the paired pages is determined. When the program address command corresponds to a first paired page, which corresponds to a first page among the pages, among the paired pages, data stored in the first page to a non-volatile memory are copied. After that, the first paired page is programmed.

Abstract translation: 提供了一种用于多级单元（MLC）闪速存储器的程序方法。 存储器阵列包括对应于各个页面的多个页面和多个配对页面。 程序方法包括以下步骤。 首先，获得程序地址命令。 接下来，确定与配对页中的任何一个对应的程序地址命令。 当程序地址命令对应于对应于页面中的第一页的第一配对页面时，在配对页面中，复制存储在第一页面中的非易失性存储器的数据。 之后，第一个配对的页面被编程。

公开(公告)号：US09136006B2

公开(公告)日：2015-09-15

申请号：US13946123

申请日：2013-07-19

Applicant: Macronix International Co., Ltd.

Inventor： Shuo-Nan Hung ,  Ji-Yu Hung

IPC: G11C16/26 ,  G11C16/24 ,  G11C16/28

CPC classification number: G11C16/26 ,  G11C16/24 ,  G11C16/28

Abstract: A method is provided for sensing data in a memory device. The memory device includes a block of memory cells coupled to a plurality of bit lines. The method includes precharging the plurality of bit lines to a first level VPRE. The method includes enabling current flow through selected memory cells on the plurality of bit lines to a reference line or to reference lines coupled to a reference voltage. The method includes preventing a voltage change as a result of the current flow on the bit lines from causing a bit line voltage to pass outside a range between the first level and a second level VKEEP, where the second level is lower than the first level and higher than the reference voltage. The method includes sensing data in the selected memory cells.

Abstract translation: 提供了一种用于感测存储器件中的数据的方法。 存储器件包括耦合到多个位线的存储器单元块。 该方法包括将多个位线预充电到第一级VPRE。 该方法包括实现电流流过多条位线上的选定存储单元到参考线或耦合到参考电压的参考线。 该方法包括防止由于位线上的电流而导致的电压变化导致位线电压超出第一电平和第二电平VKEEP之间的范围，其中第二电平低于第一电平， 高于参考电压。 该方法包括感测所选存储单元中的数据。

公开(公告)号：US08976600B2

公开(公告)日：2015-03-10

申请号：US14046428

申请日：2013-10-04

Applicant: Macronix International Co., Ltd.

Inventor： Chun-Hsiung Hung ,  Ti Wen Chen ,  Shuo-Nan Hung ,  Shih-Lin Huang

IPC: G11C16/06 ,  G11C16/16

CPC classification number: G11C16/16 ,  G11C16/08 ,  G11C16/12

Abstract: A memory circuit includes word lines coupled to a memory array, including a first set of one or more word lines deselected in an erase operation, and a second set of one or more word lines selected in the erase operation. Control circuitry couples the first set of one or more word lines deselected in the erase operation to a reference voltage, responsive to receiving an erase command for the erase operation. Some examples further include a first transistor that switchably couples a word line to a global word line, and a second transistor that switchably couples the word line to a ground voltage. The control circuitry is coupled to the first transistor and the second transistor, wherein the control circuitry has a plurality of modes including at least an erase operation. In a first mode, the first transistor couples the word line to the global word line, and the second transistor decouples the word line from the ground voltage. In a second mode, the first transistor decouples the word line from the global word line, and the second transistor couples the word line to the ground voltage.

Abstract translation: 存储电路包括耦合到存储器阵列的字线，包括在擦除操作中取消选择的一个或多个字线的第一组以及在擦除操作中选择的一个或多个字线的第二组。 响应于接收到擦除操作的擦除命令，控制电路将擦除操作中未选择的一个或多个字线的第一组耦合到参考电压。 一些示例还包括可将字线可切换地耦合到全局字线的第一晶体管，以及可切换地将字线耦合到接地电压的第二晶体管。 控制电路耦合到第一晶体管和第二晶体管，其中控制电路具有包括至少擦除操作的多个模式。 在第一模式中，第一晶体管将字线耦合到全局字线，并且第二晶体管将字线与接地电压分离。 在第二模式中，第一晶体管将字线与全局字线分离，并且第二晶体管将字线耦合到接地电压。

公开(公告)号：US20140254297A1

公开(公告)日：2014-09-11

申请号：US14036997

申请日：2013-09-25

Applicant: Macronix International Co., Ltd.

Inventor： Shuo-Nan Hung ,  Chi Lo ,  Chun-Hsiung Hung

IPC: G11C29/04

CPC classification number: G11C29/70 ,  G11C29/04 ,  G11C29/72 ,  G11C29/808 ,  G11C29/82

Abstract: An integrated circuit includes an array of memory cells that is arranged into rows, main columns, and redundant columns that perform repairs in the array. The main columns and the redundant columns are divided into row blocks. Bit lines couple the main columns to status memory indicating repair statuses of the repairs by the redundant columns. The integrated circuit receives a command, and performs an update on the status memory with the repair statuses specific to particular ones of the row blocks in a portion of the memory accessed by the command. Alternatively or in combination, the status memory has insufficient size to store the repair statuses of multiple ones of the row blocks of the main columns.

Abstract translation: 集成电路包括排列成在阵列中执行维修的行，主列和冗余列的存储器单元阵列。 主列和冗余列分为行块。 位线将主列连接到指示冗余列修复状态的状态存储器。 集成电路接收命令，并且利用该命令访问的存储器的一部分中的特定行的特定块的修复状态对状态存储器进行更新。 或者或组合地，状态存储器的尺寸不足以存储主列的多个行块的修复状态。

公开(公告)号：US20140098616A1

公开(公告)日：2014-04-10

申请号：US14105920

申请日：2013-12-13

Applicant: Macronix International Co., Ltd.

Inventor： Chun Hsiung Hung ,  Shuo-Nan Hung ,  Tseng-Yi Liu

IPC: G11C16/34

CPC classification number: G11C16/3427 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418

Abstract: Various aspects of a NAND memory include a control circuit that applies a read bias arrangement to a plurality of word lines to read a selected data value stored on a plurality of memory cells by measuring current flowing between the first end and the second end of the series of memory cells. The read bias arrangement is applied to word lines of the plurality of word lines applies only word line voltages less than a second maximum of a second threshold voltage distribution.

Abstract translation: NAND存储器的各个方面包括控制电路，该控制电路通过测量在串联的第一端和第二端之间流动的电流来将读偏置装置施加到多个字线以读取存储在多个存储单元上的选定数据值 的记忆细胞。 读取偏置布置被施加到多个字线的字线仅施加小于第二阈值电压分布的第二最大值的字线电压。