公开(公告)号：US20150311218A1

公开(公告)日：2015-10-29

申请号：US14259771

申请日：2014-04-23

Applicant: Macronix International Co., Ltd.

Inventor： Fang-Hao Hsu ,  Shih-Ping Hong ,  Hong-Ji Lee

IPC: H01L27/115 ,  H01L21/28 ,  H01L23/00 ,  H01L29/49

CPC classification number: H01L23/564 ,  H01L21/28273 ,  H01L27/11543 ,  H01L29/4933 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is described that facilitates inter-layer dielectric fill-in among transistors in a densely-configured array of an integrated circuit. An etch process that exploits a micro-loading effect to create a T-shaped profile between transistors is disclosed. The micro-loading has a negligible effect on transistors in a peripheral region of the integrated circuit.

Abstract translation: 描述了一种促进集成电路的密集配置的阵列中的晶体管之间的层间电介质填充的方法。 公开了利用微载荷效应在晶体管之间产生T形轮廓的蚀刻工艺。 微载物对集成电路的外围区域中的晶体管具有可忽略的影响。

公开(公告)号：US12048154B2

公开(公告)日：2024-07-23

申请号：US17344661

申请日：2021-06-10

Applicant: MACRONIX International Co., Ltd.

Inventor： Hong-Ji Lee ,  Tzung-Ting Han ,  Lo Yueh Lin ,  Chih-Chin Chang ,  Yu-Fong Huang ,  Yu-Hsiang Yeh

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: A memory device includes a first stack structure, a second stack structure, a channel pillar, a storage layer, and a conductive pillar. The first stack structure includes a first insulating layer and a first conductive layer located on the first insulating layer. The second stack structure is located on the first stack structure and includes a plurality of second conductive layers and a plurality of second insulating layers which alternate with each other. The channel pillar penetrates through the second stack structure and extends to the first stack structure. The storage layer is located between the channel pillar and the first stack structure and between the channel pillar and the second stack structure. The conductive pillar is located in the first conductive layer and electrically connected to the first conductive layer and the substrate.

公开(公告)号：US20160358810A1

公开(公告)日：2016-12-08

申请号：US14729843

申请日：2015-06-03

Applicant: MACRONIX International Co., Ltd.

Inventor： Fang-Hao Hsu ,  Hong-Ji Lee

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/02 ,  H01L21/311 ,  H01L21/308

CPC classification number: H01L21/76229 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28273 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32137 ,  H01L21/76232 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543 ,  H01L29/0649

Abstract: Provided is a method of fabricating a semiconductor device, including the following. A first material layer, a second material layer and a mask layer are formed on a substrate. A portion of the second material layer is removed by performing a first etching process with the mask layer as a mask, so as to expose the first material layer and form a first pattern layer and a second pattern layer. A portion of the first material layer is removed by performing a second etching process with the mask layer as a mask, so as to expose a portion of the substrate. A portion of the substrate is removed by performing a third etching process with the mask layer as a mask, so as to form first trenches and second trenches. Sidewalls of the second trenches and a surface of the substrate form at least two different angles.

Abstract translation: 提供一种制造半导体器件的方法，包括以下。 在基板上形成第一材料层，第二材料层和掩模层。 通过以掩模层作为掩模执行第一蚀刻工艺来去除第二材料层的一部分，以暴露第一材料层并形成第一图案层和第二图案层。 通过以掩模层作为掩模进行第二蚀刻工艺来去除第一材料层的一部分，以暴露基板的一部分。 通过用掩模层作为掩模执行第三蚀刻工艺来去除衬底的一部分，以便形成第一沟槽和第二沟槽。 第二沟槽的侧壁和衬底的表面形成至少两个不同的角度。

公开(公告)号：US20160190334A1

公开(公告)日：2016-06-30

申请号：US14582929

申请日：2014-12-24

Applicant: MACRONIX International Co., Ltd.

Inventor： Hong-Ji Lee ,  Han-Hui Hsu

IPC: H01L29/788 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/06 ,  H01L27/115 ,  H01L21/311

CPC classification number: H01L29/7883 ,  H01L21/31116 ,  H01L21/32135 ,  H01L21/32139 ,  H01L27/11521 ,  H01L29/0649 ,  H01L29/40114

Abstract: Provided is a memory device including a substrate, a plurality of tunneling dielectric layers, a plurality of isolation structures, and a plurality of cap layers. The tunneling dielectric layers are located on the substrate. Each isolation structure has an upper portion and a lower portion. The lower portions of the isolation structures are located in the substrate and arranged alternately with the tunneling dielectric layers along a first direction. The upper portions of the isolation structures are located on the lower portions. The cap layers are located on the upper portions. A top surface of the cap layer is a planar surface.

Abstract translation: 提供了一种存储器件，其包括衬底，多个隧道电介质层，多个隔离结构和多个覆盖层。 隧穿电介质层位于衬底上。 每个隔离结构具有上部和下部。 隔离结构的下部位于衬底中，并沿隧道电介质层与第一方向交替布置。 隔离结构的上部位于下部。 盖层位于上部。 盖层的顶表面是平坦表面。

公开(公告)号：US09305840B2

公开(公告)日：2016-04-05

申请号：US14138038

申请日：2013-12-21

Applicant: Macronix International Co., Ltd.

Inventor： Hsu-Sheng Yu ,  Hong-Ji Lee ,  N. T. Lian ,  T. H. Yang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/67

CPC classification number: H01L21/76879 ,  H01L21/67207 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A cluster tool is disclosed that can increase throughput of a wafer fabrication process by facilitating removal of barrier overhang in contact holes of contact film stacks. Individual chambers of the cluster tool provide for deposition of barrier material onto a semiconductor structure, depositing over with an amorphous carbon film (ACF), etching back the ACF, and etching a corner region of the contact hole. Removal of the barrier overhang improves the quality of metal fill-in of the contact hole. An expectedly ensuing feature entails a technique in which filling-in of the contact hole with a metal such as tungsten can be achieved with attenuated or eliminated adverse consequence.

Abstract translation: 公开了一种集群工具，其可以通过有助于去除接触膜堆叠的接触孔中的阻挡突出部来增加晶片制造工艺的生产量。 集群工具的单个室提供阻挡材料沉积到半导体结构上，用无定形碳膜（ACF）沉积，对ACF进行蚀刻，并蚀刻接触孔的拐角区域。 阻挡突出部的移除提高了接触孔的金属填充质量。 预期的随后特征需要一种技术，其中可以通过减弱或消除不利后果来实现用诸如钨的金属填充接触孔。

公开(公告)号：US09269660B2

公开(公告)日：2016-02-23

申请号：US13772121

申请日：2013-02-20

Applicant: Macronix International Co., Ltd.

Inventor： Shih-Hung Chen ,  Hang-Ting Lue ,  Hong-Ji Lee ,  Chin-Cheng Yang

IPC: H01L23/50 ,  H01L23/522 ,  H01L23/48 ,  H01L27/112 ,  H01L21/768 ,  H01L27/02 ,  H01L27/115 ,  H01L23/00 ,  H01L27/06

CPC classification number: H01L23/50 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76838 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5226 ,  H01L24/19 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/11206 ,  H01L27/11286 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/00

Abstract: A three-dimensional stacked IC device includes a stack of at least first, second, third and fourth contact levels at an interconnect region. Each contact level has a conductive layer and an insulation layer. First, second, third and fourth electrical conductors pass through portions of the stack of contact levels. The first, second, third and fourth electrical conductors are in electrical contact with the first, second, third and fourth conductive layers, respectively. A dielectric sidewall spacer circumferentially surrounds the second, third and fourth electrical conductors so that the second, third and fourth electrical conductors only electrically contact the respective second, third and fourth conductive layers.

Abstract translation: 三维堆叠IC器件包括在互连区域处的至少第一，第二，第三和第四接触电平的堆叠。 每个接触层具有导电层和绝缘层。 第一，第二，第三和第四电导体穿过接触层叠层的部分。 第一，第二，第三和第四电导体分别与第一，第二，第三和第四导电层电接触。 电介质侧壁间隔件周向地围绕第二，第三和第四电导体，使得第二，第三和第四电导体仅电相接触相应的第二，第三和第四导电层。

公开(公告)号：US20150214054A1

公开(公告)日：2015-07-30

申请号：US14162737

申请日：2014-01-24

Applicant: Macronix International Co., Ltd.

Inventor： Zusing Yang ,  Hong-Ji Lee

IPC: H01L21/16 ,  H01L21/027 ,  H01L21/02

CPC classification number: H01L21/165 ,  H01L21/02063 ,  H01L21/02068 ,  H01L21/02568 ,  H01L21/02614 ,  H01L21/02639 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/321 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76849

Abstract: Effects of copper oxide formation in semiconductor manufacture are mitigated by etching with sulfide plasmas. The plasmas form protective copper sulfide films on copper surfaces and prevent copper oxide formation. When copper oxide formation does occur, the sulfide plasmas are able to transform the copper oxide into acceptable or more conductive copper compounds. Non-oxide copper compounds are removed using clear wet strips.

Abstract translation: 半导体制造中氧化铜形成的影响通过用硫化物等离子体蚀刻来缓解。 等离子体在铜表面形成保护性硫化铜膜，防止形成铜氧化物。 当发生铜氧化物形成时，硫化物等离子体能够将氧化铜转化为可接受或更导电的铜化合物。 使用清晰的湿条除去非氧化物铜化合物。

公开(公告)号：US20150179569A1

公开(公告)日：2015-06-25

申请号：US14138007

申请日：2013-12-21

Applicant: Macronix International Co., Ltd.

Inventor： Fang-Hao Hsu ,  Hsu-Sheng Yu ,  Kuo-Feng Lo ,  Hong-Ji Lee

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76831 ,  H01L23/3192 ,  H01L23/485 ,  H01L23/53257 ,  H01L2924/00 ,  H01L2924/0002

Abstract: A method of eliminating overhang in a contact hole formed in a contact film stack is described. A liner layer is overlaid on the contact film stack, the liner also coating the contact hole. A portion of the liner is removed to expose the overhang, and the exposed overhang is removed. The liner is also used to fill-in a bowing profile of the contact hole, thereby rendering sidewalls of the contact hole smooth and straight suitable for metal fill-in while suppressing piping defects.

Abstract translation: 描述了形成在接触膜叠层中的接触孔中消除悬垂的方法。 衬垫层覆盖在接触膜叠层上，衬垫也涂覆接触孔。 衬里的一部分被去除以露出突出端，并且去除暴露的突出端。 衬套也用于填充接触孔的弯曲轮廓，从而使接触孔的侧壁平滑和直线适于金属填充，同时抑制管道缺陷。

公开(公告)号：US20130161835A1

公开(公告)日：2013-06-27

申请号：US13772121

申请日：2013-02-20

Applicant: Macronix International Co., Ltd.

Inventor： Shih-Hung Chen ,  Hang-Ting Lue ,  Hong-Ji Lee ,  Chin-Cheng Yang

IPC: H01L23/50

CPC classification number: H01L23/50 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76838 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5226 ,  H01L24/19 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/11206 ,  H01L27/11286 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/00

Abstract: A three-dimensional stacked IC device includes a stack of at least first, second, third and fourth contact levels at an interconnect region. Each contact level has a conductive layer and an insulation layer. First, second, third and fourth electrical conductors pass through portions of the stack of contact levels. The first, second, third and fourth electrical conductors are in electrical contact with the first, second, third and fourth conductive layers, respectively. A dielectric sidewall spacer circumferentially surrounds the second, third and fourth electrical conductors so that the second, third and fourth electrical conductors only electrically contact the respective second, third and fourth conductive layers.

Abstract translation: 三维堆叠IC器件包括在互连区域处的至少第一，第二，第三和第四接触电平的堆叠。 每个接触层具有导电层和绝缘层。 第一，第二，第三和第四电导体穿过接触层叠层的部分。 第一，第二，第三和第四电导体分别与第一，第二，第三和第四导电层电接触。 电介质侧壁间隔件周向地围绕第二，第三和第四电导体，使得第二，第三和第四电导体仅电相接触相应的第二，第三和第四导电层。