公开(公告)号：US11144228B2

公开(公告)日：2021-10-12

申请号：US16508729

申请日：2019-07-11

Applicant: Micron Technology, Inc.

Inventor： Andrea Martinelli ,  Christophe Vincent Antoine Laurent ,  Claudio Nava ,  Marco Defendi

IPC: G06F3/06 ,  G11C11/22 ,  G11C29/52 ,  G11C11/4091 ,  G06F11/10 ,  G11C11/408

Abstract: Methods, systems, and devices for circuit partitioning for a memory device are described. In one example, a memory device may include a set of memory tiles that each include a respective array of memory cells (e.g., in an array level or layer). Each of the memory tiles may include a respective circuit level or layer associated with circuitry configured to operate the respective array of memory cells. The memory device may also include circuitry for communicating data between the memory cells of the set of memory tiles and an input/output component. Aspects of the circuitry for communicating the data may be subdivided into repeatable blocks each configured to communicate one or more bits, and the repeatable blocks and other aspects of the circuitry for communicating the data is distributed across the circuit layer of two or more of the set of memory tiles.

公开(公告)号：US09038044B2

公开(公告)日：2015-05-19

申请号：US14098054

申请日：2013-12-05

Applicant: Micron Technology Inc.

Inventor： Massimiliano Mollichelli ,  Andrea Martinelli ,  Stefan Schippers

IPC: G06F9/45 ,  G06F12/02 ,  G06F9/445

CPC classification number: G06F12/0246 ,  G06F8/66

Abstract: Example embodiments described herein may comprise a transfer of firmware execution within a non-volatile memory device to one or more replacement instructions at least in part in response to a match between a code fetch address and an address stored in a trap address register.

Abstract translation: 本文所描述的示例性实施例可以包括至少部分地响应于代码获取地址和存储在陷阱地址寄存器中的地址之间的匹配而将非易失性存储器设备内的固件执行转移到一个或多个替换指令。

公开(公告)号：US20240304244A1

公开(公告)日：2024-09-12

申请号：US18604192

申请日：2024-03-13

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Andrea Martinelli ,  Maurizio Rizzi

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  G11C16/34

CPC classification number: G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  G11C16/3404

Abstract: Methods, systems, and devices for techniques for parallel memory cell access are described. A memory device may include multiple tiers of memory cells. During a first duration, a first voltage may be applied to a set of word lines coupled with a tier of memory cells to threshold one or more memory cells included in a first subset of memory cells of the tier. During a second duration, a second voltage may be applied to the set of word lines to write a first logic state to the one or more memory cells of the first subset and to threshold one or more memory cells included in a second subset of memory cells of the tier. During a third duration, a third voltage may be applied to the set of word lines to write a second logic state to the one or more memory cells of the second subset.

公开(公告)号：US20240274183A1

公开(公告)日：2024-08-15

申请号：US18582185

申请日：2024-02-20

Applicant: Micron Technology, Inc.

Inventor： Efrem Bolandrina ,  Andrea Martinelli ,  Christophe Vincent Antoine Laurent ,  Ferdinando Bedeschi

IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/4093

CPC classification number: G11C11/4082 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4093

Abstract: Methods, systems, and devices for parallel access in a memory array are described. A set of memory cells of a memory device may be associated with an array of conductive structures, where such structures may be coupled using a set of transistors or other switching components that are activated by a first driver. The set of memory cells may be divided into two or more subsets of memory cells, where each subset may be associated with a respective second driver for driving access currents through memory cells of the subset. Two or more of such second drivers may operate concurrently, which may support distributing current or distributing associated circuit structures across a different footprint of the memory device than other different implementations with a single such second driver.

公开(公告)号：US11830570B2

公开(公告)日：2023-11-28

申请号：US17499303

申请日：2021-10-12

Applicant: Micron Technology, Inc.

Inventor： Christopher Vincent Antoine Laurent ,  Andrea Martinelli

IPC: G06F3/00 ,  G11C7/08 ,  G06F13/16 ,  G06F3/06 ,  G11C7/10 ,  G11C8/10 ,  G11C5/14 ,  G11C7/12 ,  G11C8/08

CPC classification number: G11C7/08 ,  G06F3/0659 ,  G06F3/0688 ,  G06F13/1657 ,  G06F13/1663 ,  G06F13/1694 ,  G11C5/147 ,  G11C7/109 ,  G11C7/1063 ,  G11C7/1069 ,  G11C7/1096 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10

Abstract: Methods, systems, and devices for input/output line sharing for memory subarrays are described. I/O lines may be shared across subarrays, which may correspond to separate memory tiles. The sharing of I/O lines may allow an I/O line to carry data from one subarray in response to access commands associated with one address range, and to carry data from another subarray in response to access commands associated with another address range. In some cases, sense amplifiers and other components may also be shared across subarrays, including across subarrays in different banks. The sharing of I/O lines may, in some cases, support activating only a subset of subarrays in a bank when accessing data stored in the bank, which may provide power savings.

公开(公告)号：US11733913B2

公开(公告)日：2023-08-22

申请号：US17677586

申请日：2022-02-22

Applicant: Micron Technology, Inc.

Inventor： Christophe Vincent Antoine Laurent ,  Andrea Martinelli ,  Marco Sforzin ,  Paolo Amato

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0602 ,  G06F3/0673

Abstract: Methods, systems, and devices related to balancing data are described. Data may be communicated using an original set of bits that may be partitioned into segments. Each of the original set of bits may have a first value or a second value, where a weight of the original set of bits may be based on a quantity of the set of bits that have the first value. If the weight of the original set of bits is outside of a target weight range, a different, encoded set of bits may be used to represent the data, the encoded set of bits having a weight within the target weight range. The encoded set of bits may be identified based an inversion of the original set of bits in a one-at-a-time and cumulative fashion. The encoded set of bits may be stored in place of the original set of bits.

公开(公告)号：US20220199137A1

公开(公告)日：2022-06-23

申请号：US17563389

申请日：2021-12-28

Applicant: Micron Technology, Inc.

Inventor： Andrea Martinelli ,  Francesco Mastroianni ,  Kiyoshi Nakai

IPC: G11C11/22 ,  G11C11/4091 ,  G11C11/408 ,  G11C7/10 ,  G11C7/12 ,  G11C7/08

Abstract: Methods, systems, and devices for circuitry borrowing in memory arrays are described. In one example, a host device may transmit an access command associated with data for a first memory section to a memory device. The first memory section may be located between a second memory section and a third memory section. A first set of circuitry shared by the first memory section and the second memory section may be operated using drivers associated with the first memory section and drivers associated with the second memory section. A second set of circuitry shared by the first memory section and the third memory section may be operated using drivers associated with the first memory section and drivers associated with the third memory section. An access operation may be performed based on operating the first set of circuitry and the second set of circuitry.

公开(公告)号：US11262937B2

公开(公告)日：2022-03-01

申请号：US16865163

申请日：2020-05-01

Applicant: Micron Technology, Inc.

Inventor： Christophe Vincent Antoine Laurent ,  Andrea Martinelli ,  Marco Sforzin ,  Paolo Amato

IPC: G06F3/06

Abstract: Methods, systems, and devices related to balancing data are described. Data may be communicated using an original set of bits that may be partitioned into segments. Each of the original set of bits may have a first value or a second value, where a weight of the original set of bits may be based on a quantity of the set of bits that have the first value. If the weight of the original set of bits is outside of a target weight range, a different, encoded set of bits may be used to represent the data, the encoded set of bits having a weight within the target weight range. The encoded set of bits may be identified based an inversion of the original set of bits in a one-at-a-time and cumulative fashion. The encoded set of bits may be stored in place of the original set of bits.

公开(公告)号：US20210335407A1

公开(公告)日：2021-10-28

申请号：US17231704

申请日：2021-04-15

Applicant: Micron Technology, Inc.

Inventor： Corrado Villa ,  Andrea Martinelli

IPC: G11C11/22 ,  G06F3/06

Abstract: Methods, systems, and devices for activity-based data protection in a memory device are described. In one example, a memory device may include a set memory sections each having memory cells configured to be selectively coupled with access lines of the respective memory section. A method of operating the memory device may include determining a quantity of access operations performed on a set of sections of a memory device, selecting at least one of the sections for a voltage adjustment operation based on the determined quantity of access operations, and performing the voltage adjustment operation on the selected section. The voltage adjustment operation may include applying an equal voltage to opposite terminals of the memory cells, which may allow built-up charge, such as leakage charge accumulating from access operations of the selected memory section, to dissipate from the memory cells of the selected section.

公开(公告)号：US20210064113A1

公开(公告)日：2021-03-04

申请号：US16551597

申请日：2019-08-26

Applicant: Micron Technology, Inc.

Inventor： Christophe Vincent Antoine Laurent ,  Andrea Martinelli ,  Graziano Mirichigni

IPC: G06F1/3225 ,  G06F1/3234 ,  G06F1/3287 ,  G06F9/4401 ,  G06F9/54

Abstract: Methods, systems, and devices for architecture-based power management for a memory device are described. Aspects include operating a first memory bank within a memory device in a first mode and a second memory bank within the memory device in a second mode. The memory device may receive a power down command for the first memory bank while operating the first memory bank in the first mode and the second memory bank in the second mode and switch the first memory bank from the first mode to a first low power mode while maintaining the second memory bank in the second mode. The first low power mode corresponds to less power consumption by the first memory bank than the first mode. In some cases, switching the first memory bank from the first mode to the first low power mode includes deactivating circuitry dedicated to the first memory bank.