公开(公告)号：US20120034474A1

公开(公告)日：2012-02-09

申请号：US13264681

申请日：2010-05-26

申请人： Kimihiro Ozaki ,  Keizo Kobayashi ,  Hideki Moriguchi ,  Tomoyuki Ishida ,  Akihiko Ikegaya ,  Tomohiro Fukaya ,  Takashi Hirao ,  Takeru Nakashima ,  Mitsuo Nishimura ,  Akio Fujimura

发明人： Kimihiro Ozaki ,  Keizo Kobayashi ,  Hideki Moriguchi ,  Tomoyuki Ishida ,  Akihiko Ikegaya ,  Tomohiro Fukaya ,  Takashi Hirao ,  Takeru Nakashima ,  Mitsuo Nishimura ,  Akio Fujimura

IPC分类号： B32B15/04 ,  B32B19/00

CPC分类号： B23K31/025 ,  B23B27/18 ,  B23B2226/125 ,  B23B2226/315 ,  B23B2240/00 ,  B23K1/0008 ,  B23K1/19 ,  B23K20/008 ,  B23K20/023 ,  B23K20/16 ,  B23K20/22 ,  B23K35/325 ,  B23K35/327 ,  B23K2101/20 ,  B23K2101/34 ,  B23K2103/18 ,  B23K2103/52 ,  Y10T428/31678

摘要： A joined product according to the present invention is a joined product including a cemented carbide sintered compact serving as a first material to be joined and a cBN sintered compact or a diamond sintered compact serving as a second material to be joined. The first material to be joined and the second material to be joined are joined by a joining material that forms a liquid phase at a temperature exceeding 800° C. and lower than 1000° C. and that is placed between the first material to be joined and the second material to be joined. The first material to be joined and the second material to be joined are joined by resistance heating and pressing at a pressure of 0.1 to 200 MPa.

摘要翻译： 根据本发明的接合产品是包括用作第一接合材料的硬质合金烧结体和作为第二接合材料的cBN烧结体或金刚石烧结体的接合体。 要接合的第一材料和待接合的第二材料通过在超过800℃且低于1000℃的温度下形成液相的接合材料接合，并且被放置在待接合的第一材料之间 和第二待接合材料。 第一待接合材料和第二待接合材料通过电阻加热和压力为0.1〜200MPa的条件进行接合。

公开(公告)号：US07928505B2

公开(公告)日：2011-04-19

申请号：US12326392

申请日：2008-12-02

申请人： Takashi Hirao ,  Takayuki Hashimoto ,  Noboru Akiyama

发明人： Takashi Hirao ,  Takayuki Hashimoto ,  Noboru Akiyama

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7802 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

摘要： The vertical trench MOSFET comprises: an N type epitaxial region formed on an upper surface of an N+ type substrate having a drain electrode on a lower surface thereof; a gate trench extending from a front surface into the N type epitaxial region; a gate electrode positioned in the gate trench so as to interpose an insulator; a channel region formed on the N type epitaxial region; a source region formed on the channel region; a source electrode formed on the source region; a source trench extending from the front surface into the N type epitaxial region; and a trench-buried source electrode positioned in the source trench so as to interpose an insulator, wherein the source electrode contacts with the trench-buried source electrode.

摘要翻译： 垂直沟槽MOSFET包括：形成在其下表面上具有漏电极的N +型衬底的上表面上的N型外延区域; 栅极沟槽，其从前表面延伸到N型外延区域; 位于所述栅极沟槽中以便插入绝缘体的栅电极; 形成在N型外延区上的沟道区; 形成在沟道区上的源极区; 形成在源极区上的源电极; 源极沟槽，其从前表面延伸到N型外延区域; 以及位于所述源极沟槽中以便插入绝缘体的沟槽埋入式源电极，其中所述源电极与所述沟槽埋入式源极接触。

公开(公告)号：US20090015224A1

公开(公告)日：2009-01-15

申请号：US12171347

申请日：2008-07-11

申请人： Takashi Hirao ,  Takayuki Hashimoto ,  Masaki Shiraishi

发明人： Takashi Hirao ,  Takayuki Hashimoto ,  Masaki Shiraishi

IPC分类号： H02M3/156

CPC分类号： H02M3/158 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/49175 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/30107 ,  H03K17/162 ,  H03K17/6871 ,  H03K19/018521 ,  H03K2217/0081 ,  H01L2924/00

摘要： A DC-DC converter that prevents self turn-on and improves the power efficiency is provided. In a non-insulated DC-DC converter, self turn-on is prevented by applying a negative voltage between a gate and a source of a low side MOSFET by the use of a capacitor for generating negative voltage when the low side MOSFET is in an OFF state. Also, when the low side MOSFET is in an ON state due to the capacitor for generating negative voltage, a positive voltage applied between the gate and the source of the low side MOSFET does not drop from a voltage of a gate driving DC power source that is supplied from a gate power input terminal. Therefore, the power efficiency is improved.

摘要翻译： 提供了防止自身接通并提高功率效率的DC-DC转换器。 在非绝缘DC-DC转换器中，通过在低侧MOSFET处于低压MOSFET的栅极和源极之间通过使用用于产生负电压的电容器施加负电压来防止自身接通 OFF状态。 此外，由于用于产生负电压的电容器，当低端MOSFET处于导通状态时，施加在低侧MOSFET的栅极和源极之间的正电压不会从栅极驱动DC电源的电压下降， 由栅极电源输入端子提供。 因此，功率效率得到提高。

公开(公告)号：US20070187678A1

公开(公告)日：2007-08-16

申请号：US11704838

申请日：2007-02-09

申请人： Takashi Hirao ,  Mamoru Furuta ,  Hiroshi Furuta ,  Tokiyoshi Matsuda ,  Takahiro Hiramatsu

发明人： Takashi Hirao ,  Mamoru Furuta ,  Hiroshi Furuta ,  Tokiyoshi Matsuda ,  Takahiro Hiramatsu

IPC分类号： H01L29/10

CPC分类号： H01L21/02422 ,  H01L21/02491 ,  H01L21/02494 ,  H01L21/02554 ,  H01L21/02595 ,  H01L21/02609 ,  H01L21/02631 ,  H01L29/04 ,  H01L29/045 ,  H01L29/4908 ,  H01L29/7869 ,  H01L29/78693

摘要： A semiconductor device includes an oxide semiconductor thin film layer primarily including zinc oxide having at least one orientation other than (002) orientation. The zinc oxide may have a mixed orientation including (002) orientation and (101) orientation. Alternatively, the zinc oxide may have a mixed orientation including (100) orientation and (101) orientation.

摘要翻译： 半导体器件包括氧化物半导体薄膜层，其主要包括具有除（002）取向之外的至少一个取向的氧化锌。 氧化锌可以具有包括（002）取向和（101）取向的混合取向。 或者，氧化锌可以具有包括（100）取向和（101）取向的混合取向。

公开(公告)号：US4861729A

公开(公告)日：1989-08-29

申请号：US088216

申请日：1987-08-24

申请人： Genshu Fuse ,  Takashi Hirao ,  Takashi Ohzone

发明人： Genshu Fuse ,  Takashi Hirao ,  Takashi Ohzone

IPC分类号： H01L21/223

CPC分类号： H01L21/2236

摘要： A method in which in order to dope impurities, with excellent controllability, into a sidewall of a trench formed in a semiconductor substrate, plasma is generated in a gas including the impurities and the semiconductor substrate is disposed in or near the plasma, so that the impurities may be doped into the sidewall of the trench uniformly and at high precision of concentration control; wherein one of a duluted B.sub.2 H.sub.6 gas and diluted AsH.sub.3 gas is chosen as the gas of the plasma, whereby one of B and As as the impurities directly enters the sidewall of the trench without first passing through a film.

摘要翻译： 为了将具有优异的可控性的杂质掺杂到在半导体衬底中形成的沟槽的侧壁中的方法中，在包括杂质的气体中产生等离子体，并且半导体衬底设置在等离子体中或其附近，使得 杂质可以均匀地并且以高精度的浓度控制被掺杂到沟槽的侧壁中; 其中选择一个掺杂的B2H6气体和稀释的AsH3气体作为等离子体的气体，由此作为杂质的B和As中的一个直接进入沟槽的侧壁，而不首先通过膜。

公开(公告)号：US09251055B2

公开(公告)日：2016-02-02

申请号：US13599087

申请日：2012-08-30

申请人： Shinji Yonezawa ,  Takashi Hirao ,  Hirokuni Yano ,  Mitsunori Tadokoro ,  Hiroki Matsudaira ,  Akira Sawaoka

发明人： Shinji Yonezawa ,  Takashi Hirao ,  Hirokuni Yano ,  Mitsunori Tadokoro ,  Hiroki Matsudaira ,  Akira Sawaoka

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F2212/7205 ,  G06F2212/7209 ,  G11C2211/5641

摘要： A memory system in embodiments includes a nonvolatile semiconductor memory that stores user data, a forward lookup address translation table and a reverse lookup address translation table, and a controller. The controller is configured to determine that the user data stored in the nonvolatile semiconductor memory is valid or invalid based on these two tables. The controller may perform data organizing of selecting data determined valid and rewriting the data in a new block. The controller may perform write processing and rewriting processing to the new block alternately at a predetermined ratio. The controller may determine whether a predetermined condition is satisfied on a basis of addresses included in write requests and write data in the MLC mode when the condition is satisfied and write data in the SLC mode when the condition is not satisfied.

摘要翻译： 实施例中的存储器系统包括存储用户数据的非易失性半导体存储器，正向查找地址转换表和反向查找地址转换表以及控制器。 控制器被配置为基于这两个表来确定存储在非易失性半导体存储器中的用户数据有效或无效。 控制器可以执行数据组织，选择确定有效的数据并在新的块中重写数据。 控制器可以以预定的比例交替地对新的块执行写入处理和重写处理。 当条件满足时，控制器可以基于写入请求中包括的地址和写入数据来确定是否满足预定条件，并且当条件不满足时将控制器写入SLC模式中的数据。

公开(公告)号：US08901838B2

公开(公告)日：2014-12-02

申请号：US13560613

申请日：2012-07-27

申请人： Noboru Akiyama ,  Takayuki Hashimoto ,  Takashi Hirao ,  Nobuyoshi Matsuura ,  Hideo Ishii

发明人： Noboru Akiyama ,  Takayuki Hashimoto ,  Takashi Hirao ,  Nobuyoshi Matsuura ,  Hideo Ishii

IPC分类号： H05B37/02 ,  H01L29/78 ,  H05B33/08 ,  G09G3/34 ,  H01L29/06 ,  H01L29/417

CPC分类号： H01L29/7813 ,  G09G3/342 ,  G09G2320/064 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/41766 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7815 ,  H05B33/0818 ,  H05B33/0827 ,  H05B33/089 ,  Y02B20/347

摘要： The semiconductor device is included in the LED driving circuit (current regulator) of driving the LED array (with series-connected number m×parallel-connected number n), and is formed of a plurality (n pieces) of LED driving devices of controlling a current (constant-current driving) flowing in each string. A vertical semiconductor device, for example, a vertical MOSFET is used as the LED driving device. Both of a main device functioning as a constant-current driving device and a subsidiary device functioning as a circuit-breaking switch during dimming are formed inside a chip of the device, which are formed of the vertical semiconductor devices. In a first surface of the device, each source region of the main device and the subsidiary device is formed so as to be insulated from each other through an isolation region.

摘要翻译： 半导体器件包括在驱动LED阵列（串联数字×并联数n）的LED驱动电路（电流调节器）中，并且由多个（n个）LED驱动装置形成， 在每个串中流动的电流（恒流驱动）。 使用垂直半导体器件，例如垂直MOSFET作为LED驱动器件。 作为恒流驱动装置的主装置和在调光期间用作断路开关的辅助装置都形成在由垂直半导体装置形成的装置的芯片的内部。 在装置的第一表面中，主装置和附属装置的每个源区形成为通过隔离区彼此绝缘。

公开(公告)号：US08120345B2

公开(公告)日：2012-02-21

申请号：US12388819

申请日：2009-02-19

申请人： Noboru Akiyama ,  Takayuki Hashimoto ,  Takashi Hirao ,  Koji Tateno ,  Takuya Ishigaki

发明人： Noboru Akiyama ,  Takayuki Hashimoto ,  Takashi Hirao ,  Koji Tateno ,  Takuya Ishigaki

IPC分类号： G05F1/00

CPC分类号： H02M3/156 ,  H02M2001/0025

摘要： A semiconductor device for control applied to a constant-voltage power supply device includes a digital-analog converter circuit which outputs a reference voltage corresponding to a value of a first register with taking an output voltage of a reference voltage source as a criterial reference voltage, and generates a control signal for driving a power semiconductor device based on an output voltage of an error amplifier which differentially amplifies a feedback voltage obtained by resistive-dividing on an output voltage of the constant-voltage power supply device and the reference voltage. An analog-digital converter circuit which converts the feedback voltage to a digital value with taking the output voltage of the constant-voltage power supply device as a reference voltage is provided, and based on the output, a value of a first register is corrected so as to offset an effect of an error in voltage dividing ratio of a voltage dividing resistor circuit.

摘要翻译： 一种应用于恒压电源装置的控制用半导体装置，具备数模转换电路，该数模转换电路以取参考电压源的输出电压作为标准参考电压，输出与第一寄存器的值相对应的基准电压， 并且基于误差放大器的输出电压产生用于驱动功率半导体器件的控制信号，所述误差放大器的差分放大通过对所述恒压电源装置的输出电压进行电阻分压而获得的反馈电压和所述参考电压。 提供了一种模拟数字转换器电路，其将采取恒压电源装置的输出电压的反馈电压转换为数字值作为参考电压，并且基于该输出，第一寄存器的值被校正为 以抵消分压电阻电路的分压比的误差的影响。

公开(公告)号：US08018255B2

公开(公告)日：2011-09-13

申请号：US12171347

申请日：2008-07-11

申请人： Takashi Hirao ,  Takayuki Hashimoto ,  Masaki Shiraishi

发明人： Takashi Hirao ,  Takayuki Hashimoto ,  Masaki Shiraishi

IPC分类号： H03K3/00

CPC分类号： H02M3/158 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/49175 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/30107 ,  H03K17/162 ,  H03K17/6871 ,  H03K19/018521 ,  H03K2217/0081 ,  H01L2924/00

摘要： A DC-DC converter in which self turn-on can be prevented and can improve power efficiency. In a non-insulated DC-DC converter, self turn-on is prevented by applying a negative voltage between a gate and a source of a low side MOSFET by the use of a capacitor for generating negative voltage when the low side MOSFET is in an OFF state. Also, when the low side MOSFET is in an ON state due to the capacitor for generating negative voltage, a positive voltage applied between the gate and the source of the low side MOSFET does not drop from a voltage of a gate driving DC power source that is supplied from a gate power input terminal. Therefore, the power efficiency is improved.

摘要翻译： 可以防止自我接通并可提高功率效率的DC-DC转换器。 在非绝缘DC-DC转换器中，通过在低侧MOSFET处于低压MOSFET的栅极和源极之间通过使用用于产生负电压的电容器施加负电压来防止自身接通 OFF状态。 此外，由于用于产生负电压的电容器，当低端MOSFET处于导通状态时，施加在低侧MOSFET的栅极和源极之间的正电压不会从栅极驱动DC电源的电压下降， 由栅极电源输入端子提供。 因此，功率效率得到提高。

公开(公告)号：US07981734B2

公开(公告)日：2011-07-19

申请号：US12499559

申请日：2009-07-08

申请人： Mamoru Furuta ,  Takashi Hirao ,  Hiroshi Furuta ,  Tokiyoshi Matsuda ,  Takahiro Hiramatsu ,  Hiromitsu Ishii ,  Hitoshi Hokari ,  Motohiko Yoshida

发明人： Mamoru Furuta ,  Takashi Hirao ,  Hiroshi Furuta ,  Tokiyoshi Matsuda ,  Takahiro Hiramatsu ,  Hiromitsu Ishii ,  Hitoshi Hokari ,  Motohiko Yoshida

IPC分类号： H01L21/302

CPC分类号： H01L29/7869 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78618

摘要： A manufacturing method of a thin film transistor includes forming a pair of source/drain electrodes on a substrate, such that the source/drain electrodes define a gap therebetween; forming low resistance conductive thin films, which define a gap therebetween, on the source/drain electrodes; and forming an oxide semiconductor thin film layer on upper surface of the low resistance conductive thin films and in the gap defined between the low resistance conductive thin films so that the oxide semiconductor thin film layer functions as a channel. The low resistance conductive thin films and the oxide semiconductor thin film layer are etched so that side surfaces of the resistance conductive thin films and corresponding side surfaces of the oxide semiconductor thin film layer coincide with each other in a channel width direction of the channel. A gate electrode is mounted over the oxide semiconductor thin film layer.

摘要翻译： 薄膜晶体管的制造方法包括在基板上形成一对源极/漏极，使得源极/漏极在其间限定间隙; 在源/漏电极上形成限定它们之间的间隙的低电阻导电薄膜; 以及在低电阻导电薄膜的上表面和限定在低电阻导电薄膜之间的间隙中形成氧化物半导体薄膜层，使得氧化物半导体薄膜层用作沟道。 蚀刻低电阻导电薄膜和氧化物半导体薄膜层，使得电阻导电薄膜的侧表面和氧化物半导体薄膜层的相应侧表面在沟道的沟道宽度方向上彼此重合。 栅电极安装在氧化物半导体薄膜层上。