公开(公告)号：US20140159105A1

公开(公告)日：2014-06-12

申请号：US13831780

申请日：2013-03-15

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Kee Ju Um ,  In Hyuk Song ,  Chang Su Jang ,  Jae Hoon Park ,  Dong Soo Seo

IPC: H01L29/739

CPC classification number: H01L29/7397 ,  H01L29/1095 ,  H01L29/41741

Abstract: Disclosed herein is a power semiconductor device, including: a drift layer formed on the first surface of the semiconductor substrate, a well layer of a first conductive type, formed on the drift layer, a trench formed to reach the drift layer through the well layer, a first electrode formed in the trench, a second conductive type of second electrode region formed on the well layer, including a first region contacting the trench in a perpendicular direction and a second region spaced apart from the trench in a parallel direction and being perpendicular to the first region, a first conductive type of second electrode region formed to contact a side surface of the second conductive type of second electrode region, and a second electrode formed on the well layer and electrically connected to the second conductive type of second electrode region and the first conductive type of second electrode region.

Abstract translation: 本文公开了一种功率半导体器件，包括：形成在半导体衬底的第一表面上的漂移层，形成在漂移层上的第一导电类型的阱层，形成为通过阱层到达漂移层的沟槽 ，形成在沟槽中的第一电极，形成在阱层上的第二导电类型的第二电极区域，包括在垂直方向上接触沟槽的第一区域和在平行方向上与沟槽间隔开的第二区域，并且垂直 形成为与第二导电类型的第二电极区域的侧表面接触的第一导电类型的第二电极区域和形成在阱层上并与第二导电类型的第二电极区域电连接的第二电极 和第一导电类型的第二电极区域。

公开(公告)号：US09356116B2

公开(公告)日：2016-05-31

申请号：US13890680

申请日：2013-05-09

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jaehoon Park ,  In Hyuk Song ,  Dong Soo Seo ,  Kwang Soo Kim ,  Kee Ju Um

IPC: H01L29/66 ,  H01L29/739 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/768 ,  H01L29/78 ,  H01L51/05 ,  H01L27/08 ,  H01L27/092 ,  H01L31/111

CPC classification number: H01L29/66348 ,  H01L27/0817 ,  H01L27/088 ,  H01L27/0921 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1079 ,  H01L29/41733 ,  H01L29/4232 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/66477 ,  H01L29/66484 ,  H01L29/66954 ,  H01L29/7393 ,  H01L29/7397 ,  H01L29/768 ,  H01L29/78 ,  H01L31/111 ,  H01L31/1113 ,  H01L51/0512

Abstract: There is provided a power semiconductor device, including a first conductive type drift layer; a second conductive type body layer formed on the drift layer, a second conductive type collector layer formed below the drift layer; a first gate formed by penetrating through the body layer and a portion of the drift layer, a first conductive type emitter layer formed in the body layer and formed to be spaced apart from the first gate, a second gate covering upper portions of the body layer and the emitter layer and formed as a flat type gate on the first gate, and a segregation stop layer formed between contact surfaces of the first and second gates with the body layer, the emitter layer, and the drift layer.

Abstract translation: 提供了一种功率半导体器件，包括第一导电型漂移层; 形成在漂移层上的第二导电型体层，形成在漂移层下面的第二导电型集电极层; 通过贯穿本体层和漂移层的一部分而形成的第一栅极，形成在主体层中并形成为与第一栅极间隔开的第一导电型发射极层，覆盖主体层的上部的第二栅极 和发射极层，并且在第一栅极上形成为平面型栅极，以及在第一和第二栅极的接触表面之间形成的偏析阻挡层，其具有主体层，发射极层和漂移层。

公开(公告)号：US09318423B2

公开(公告)日：2016-04-19

申请号：US14572763

申请日：2014-12-16

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Kwang Soo Kim ,  Kee Ju Um ,  Suk Ho Lee ,  Joon Seok Chae

IPC: H01L23/495 ,  H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L25/18 ,  H01L23/31

CPC classification number: H01L23/49548 ,  H01L23/3107 ,  H01L23/49531 ,  H01L23/49537 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48108 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48177 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: There is provided a leadless package type power semiconductor module. According to an exemplary embodiment of the present disclosure, the leadless package type power semiconductor module includes: connection terminals of a surface mounting type (SMT) formed at edges at which respective sides of four surfaces meet each other; a first mounting area connected to the connection terminals through a bridge to be disposed at a central portion thereof and mounted with power devices or control ICs electrically connected to the power devices to control the power devices; and second mounting areas formed between the connection terminals and mounted with the power devices or the control ICs, wherein the first mounting area is disposed at a different height from the second mounting area through the bridge to generate a phase difference from the second mounting area. Therefore, it is possible to implement a high-integration, high-performance, and small power semiconductor module by applying a three-dimensional structure deviating from a one-dimensional flat structure.

Abstract translation: 提供无引线封装型功率半导体模块。 根据本公开的示例性实施例，无引线封装型功率半导体模块包括：形成在四个表面的相应边缘彼此相遇的边缘处的表面安装型（SMT）的连接端子; 第一安装区域，其通过桥接器连接到连接端子，以布置在其中心部分，并安装有电连接到电力设备的功率器件或控制IC以控制功率器件; 以及形成在所述连接端子之间并且安装有所述功率器件或所述控制IC的第二安装区域，其中所述第一安装区域设置在与所述第二安装区域不同的高度，以通过所述桥接器产生与所述第二安装区域的相位差。 因此，可以通过应用偏离一维平面结构的三维结构来实现高集成度，高性能和小功率半导体模块。

公开(公告)号：US20150214140A1

公开(公告)日：2015-07-30

申请号：US14572763

申请日：2014-12-16

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Kwang Soo Kim ,  Kee Ju Um ,  SukHo Lee ,  Joon Seok Chae

IPC: H01L23/495 ,  H01L23/31 ,  H01L25/18 ,  H01L23/00

CPC classification number: H01L23/49548 ,  H01L23/3107 ,  H01L23/49531 ,  H01L23/49537 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48108 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48177 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: There is provided a leadless package type power semiconductor module. According to an exemplary embodiment of the present disclosure, the leadless package type power semiconductor module includes: connection terminals of a surface mounting type (SMT) formed at edges at which respective sides of four surfaces meet each other; a first mounting area connected to the connection terminals through a bridge to be disposed at a central portion thereof and mounted with power devices or control ICs electrically connected to the power devices to control the power devices; and second mounting areas formed between the connection terminals and mounted with the power devices or the control ICs, wherein the first mounting area is disposed at a different height from the second mounting area through the bridge to generate a phase difference from the second mounting area. Therefore, it is possible to implement a high-integration, high-performance, and small power semiconductor module by applying a three-dimensional structure deviating from a one-dimensional flat structure.

Abstract translation: 提供无引线封装型功率半导体模块。 根据本公开的示例性实施例，无引线封装型功率半导体模块包括：形成在四个表面的相应边缘彼此相遇的边缘处的表面安装型（SMT）的连接端子; 第一安装区域，其通过桥接器连接到连接端子，以布置在其中心部分，并安装有电连接到电力设备的功率器件或控制IC以控制功率器件; 以及形成在所述连接端子之间并且安装有所述功率器件或所述控制IC的第二安装区域，其中所述第一安装区域设置在与所述第二安装区域不同的高度，以通过所述桥接器产生与所述第二安装区域的相位差。 因此，可以通过应用偏离一维平面结构的三维结构来实现高集成度，高性能和小功率半导体模块。

公开(公告)号：US20150144993A1

公开(公告)日：2015-05-28

申请号：US14292297

申请日：2014-05-30

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Kee Ju Um ,  In Hyuk Song ,  Jae Hoon Park ,  Chang Su Jang ,  Ji Yeon Oh

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L29/0661 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/407 ,  H01L29/7397

Abstract: A power semiconductor device may include: an active region having a current flowing through a channel formed therein at the time of a turn-on operation of the power semiconductor device; a termination region formed in the vicinity of the active region; a plurality of first trenches formed lengthwise in one direction in the active region; and at least one or more second trenches formed lengthwise in one direction in the termination region. The second trench has a depth deeper than that of the first trench.

Abstract translation: 功率半导体器件可以包括：在功率半导体器件的导通操作时具有流过其中形成的沟道的电流的有源区; 形成在有源区附近的端接区域; 多个第一沟槽，在有源区域中沿一个方向纵向形成; 以及至少一个或多个第二沟槽，其在端接区域中沿一个方向纵向形成。 第二沟槽的深度比第一沟槽深。

公开(公告)号：US09019735B2

公开(公告)日：2015-04-28

申请号：US13762724

申请日：2013-02-08

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： In Wha Jeong ,  Kee Ju Um ,  Bum Seok Suh ,  Kwang Soo Kim ,  Min Gyu Park

IPC: H02M7/219 ,  H02M1/42 ,  H02M3/158 ,  H02M1/34

CPC classification number: H02M1/42 ,  H02M1/4225 ,  H02M3/1584 ,  H02M2001/342 ,  H02M2003/1586 ,  Y02B70/126 ,  Y02B70/1491 ,  Y02P80/112

Abstract: A power factor correction circuit may include a boost converter circuit in which a plurality of boost circuits including a boost inductor, a rectifying diode, and a boost switch are connected with each other; and a snubber circuit including a snubber inductor and a snubber switch so as to snubber the boost converter circuit. The snubber inductor may be controlled so as to be turned on before the boost inductor is turned on to apply zero voltage to the boost inductor. It is possible to reduce switching loss occurring when the boost switch is turned on and increase efficiency of an AC-DC power supply apparatus.

Abstract translation: 功率因数校正电路可以包括升压转换器电路，其中包括升压电感器，整流二极管和升压开关的多个升压电路彼此连接; 以及包括缓冲电感器和缓冲开关的缓冲电路，以便缓冲升压转换器电路。 缓冲电感器可以被控制为在升压电感器接通之前导通，以向升压电感器施加零电压。 可以减小升压开关导通时的开关损耗，提高AC-DC电源装置的效率。

公开(公告)号：US20150076595A1

公开(公告)日：2015-03-19

申请号：US14331603

申请日：2014-07-15

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Jae Kyu Sung ,  Jae Hoon Park ,  Kee Ju Um ,  In Hyuk Song

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7813 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/7397

Abstract: A power semiconductor device may include: a first conductive type drift layer in which trench gates are formed; a second conductive type well region formed on the drift layer so as to contact the trench gate; a first conductive type source region formed on the well region so as to contact the trench gate; and a device protection region formed below a height of a lowermost portion of the source region in a height direction.

Abstract translation: 功率半导体器件可以包括：形成有沟槽栅极的第一导电型漂移层; 形成在所述漂移层上以与所述沟槽栅极接触的第二导电类型阱区; 形成在所述阱区上以便与所述沟槽栅极接触的第一导电型源极区; 以及在高度方向上形成在源极区域的最下部的高度以下的器件保护区域。

公开(公告)号：US20150041884A1

公开(公告)日：2015-02-12

申请号：US14301328

申请日：2014-06-10

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： In Hyuk Song ,  Jae Hoon Park ,  Kee Ju Um ,  Dong Soo Seo

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/063 ,  H01L29/0611 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802

Abstract: There is provided a power semiconductor device including: a first semiconductor region of a first conductivity type; second semiconductor regions formed in the first semiconductor region and being of a second conductivity type; a well region formed above the second semiconductor regions and being of the second conductivity type; and a source region formed in the well region and being of the first conductivity type, wherein the second semiconductor regions include 1 to n layers formed from a lower portion of the device extending a in a direction of height of the device, and in the case that the widest width of the of the second semiconductor region of the nth layer is Pn, P1

Abstract translation: 提供了一种功率半导体器件，包括：第一导电类型的第一半导体区域; 形成在第一半导体区域中并且是第二导电类型的第二半导体区域; 形成在第二半导体区域上方并且是第二导电类型的阱区; 以及形成在阱区中并且是第一导电类型的源区，其中第二半导体区包括从器件的下部在器件的高度方向延伸的1至n层，并且在该情况下 第n层的第二半导体区域的最宽宽度为Pn，P1

公开(公告)号：US20140119070A1

公开(公告)日：2014-05-01

申请号：US13762724

申请日：2013-02-08

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： In Wha Jeong ,  Kee Ju Um ,  Bum Seok Suh ,  Kwang Soo Kim ,  Min Gyu Park

IPC: H02M1/14 ,  H02M1/42

CPC classification number: H02M1/42 ,  H02M1/4225 ,  H02M3/1584 ,  H02M2001/342 ,  H02M2003/1586 ,  Y02B70/126 ,  Y02B70/1491 ,  Y02P80/112

Abstract: Disclosed herein is a power factor correction circuit, including: a boost converter circuit in which a plurality of boost circuits including a boost inductor, a rectifying diode, and a boost switch are connected with each other; and a snubber circuit including a snubber inductor and a snubber switch so as to snubber the boost converter circuit. The snubber inductor is controlled so as to be turned on before the boost inductor is turned on to apply zero voltage to the boost inductor. It is possible to reduce switching loss occurring when the boost switch is turned on and increase efficiency of an AC-DC power supply apparatus.

Abstract translation: 本文公开了一种功率因数校正电路，包括：升压转换器电路，其中包括升压电感器，整流二极管和升压开关的多个升压电路彼此连接; 以及包括缓冲电感器和缓冲开关的缓冲电路，以便缓冲升压转换器电路。 缓冲电感器被控制为在升压电感器接通之前导通，以向升压电感器施加零电压。 可以减小升压开关导通时的开关损耗，提高AC-DC电源装置的效率。

公开(公告)号：US20140117374A1

公开(公告)日：2014-05-01

申请号：US13758946

申请日：2013-02-04

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Hoon Park ,  Chang Su Jang ,  In Hyuk Song ,  Kee Ju Um ,  Dong Soo Seo

IPC: H01L29/20 ,  H01L29/00

CPC classification number: H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/861 ,  H01L29/872

Abstract: Disclosed herein is a semiconductor device including: a base substrate; a first nitride semiconductor layer formed on the base substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer; a cathode electrode formed on one side of the second nitride semiconductor layer; an anode electrode having one end and the other end, one end being recessed at the other side of the second nitride semiconductor layer up to a predetermined depth, and the other end being spaced apart from the cathode electrode and formed to be extended up to an upper portion of the cathode electrode; and an insulating film formed on the second nitride semiconductor layer between the anode electrode and the cathode electrode so as to cover the cathode electrode.

Abstract translation: 本文公开了一种半导体器件，包括：基底; 形成在所述基底基板上的第一氮化物半导体层; 形成在第一氮化物半导体层上的第二氮化物半导体层; 阴极，形成在所述第二氮化物半导体层的一侧上; 具有一端和另一端的阳极，一端在第二氮化物半导体层的另一侧凹入达预定深度，另一端与阴极间隔开并形成为延伸至 阴极电极的上部; 以及在阳极电极和阴极电极之间形成在第二氮化物半导体层上以覆盖阴极电极的绝缘膜。