公开(公告)号：US20230134276A1

公开(公告)日：2023-05-04

申请号：US18091509

申请日：2022-12-30

Applicant: SAMSUNG ELECTRONICS Co, Ltd.

Inventor： Yonghwan Kwon

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L23/00

Abstract: A fan-out semiconductor package includes: a support wiring structure including a support wiring conductive structure, a plurality of support wiring insulating layers including a first support wiring insulating layer having a recess area and a second support wiring insulating layer on the first support wiring insulating layer and enveloping the support wiring conductive structure, a pad layer enveloped by the second support wiring insulating layer and connected to the support wiring conductive structure, and an under-bump metallurgy (UBM) layer enveloped by the first support wiring insulating layer and connected to the pad layer; and a semiconductor chip on the support wiring structure, wherein the UBM layer includes a body portion and a protrusion protruding from the body portion and arranged in the recess area.

公开(公告)号：US20220068731A1

公开(公告)日：2022-03-03

申请号：US17245628

申请日：2021-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghwan Kwon

IPC: H01L21/66 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes a semiconductor chip having first and second contact pads that are alternately arranged in a first direction; an insulating film having first openings respectively defining first pad regions of first contact pads, and second openings respectively defining second pad regions of the second contact pads; first and second conductive capping layers on the first and second pad regions, respectively; and an insulating layer on the insulating film, and having first and second contact holes respectively connected to the first and second conductive capping layers. Each of the first and second pad regions includes a bonding region having a first width and a probing region having a second width, greater than the first width, and each of the second pad regions is arranged in a direction that is opposite to each of the plurality of first pad regions.

公开(公告)号：US09972580B2

公开(公告)日：2018-05-15

申请号：US15345779

申请日：2016-11-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghwan Kwon ,  Seung-Kwan Ryu

IPC: H01L23/00 ,  H01L21/3105 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/31058 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/29147 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/37001 ,  H01L2224/83

Abstract: A semiconductor package includes a stack structure, a mold layer disposed on at least one sidewall of the stack structure, a redistribution line electrically connected to the stack structure, and an external terminal electrically connected to the redistribution line. The stack structure includes a semiconductor chip having an active surface and a non-active surface opposite to the active surface. A dummy substrate is disposed on the non-active surface of the semiconductor chip. An adhesive layer is disposed between the dummy substrate and the semiconductor chip. The mold layer includes a top surface adjacent to the redistribution line and a bottom surface opposite to the top surface. The dummy substrate is exposed through the bottom surface of the mold layer.

公开(公告)号：US09653372B2

公开(公告)日：2017-05-16

申请号：US14824394

申请日：2015-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghwan Kwon

IPC: H01L21/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/563 ,  H01L21/565 ,  H01L21/566 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3178 ,  H01L23/3185 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/96 ,  H01L25/065 ,  H01L25/50 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/92124 ,  H01L2224/92224 ,  H01L2224/92225 ,  H01L2224/92244 ,  H01L2225/06544 ,  H01L2924/00

Abstract: A method for fabricating a fan-out wafer level package includes disposing a first semiconductor chip on a dummy substrate, forming a mold substrate on the first semiconductor chip and the dummy substrate, removing the dummy substrate to expose the first semiconductor chip, disposing a second semiconductor chip on the exposed first semiconductor chip, forming an insulating layer on the second semiconductor chip, the first semiconductor chip, and the mold substrate, and forming a plurality of redistribution lines that electrically connects the first semiconductor chip and the second semiconductor chip through the insulating layer.

公开(公告)号：US09159688B2

公开(公告)日：2015-10-13

申请号：US14170809

申请日：2014-02-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Yun Myung ,  Yonghwan Kwon

IPC: H01L23/00 ,  H01L23/31

CPC classification number: H01L24/13 ,  H01L21/563 ,  H01L23/3128 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11906 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/13655 ,  H01L2224/1601 ,  H01L2224/16058 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2924/15311 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A semiconductor device includes a bonding pad on a semiconductor substrate, a bump on the bonding pad, a solder on the bump, and an anti-wetting layer between the bump and the solder extending along a sidewall of the bump, the anti-wetting layer having a first thickness T1 along the sidewall of the bump closer to the solder and a second thickness T2 along the sidewall of the bump closer to the bonding pad, wherein T2

Abstract translation: 一种半导体器件包括：半导体衬底上的焊盘，焊盘上的凸块，凸块上的焊料，以及沿着凸块的侧壁延伸的凸块和焊料之间的防潮湿层，防湿层 沿凸块的靠近焊料的侧壁具有第一厚度T1，沿凸点的侧壁更靠近焊盘的第二厚度T2，其中T2