公开(公告)号：US20170084754A1

公开(公告)日：2017-03-23

申请号：US15262660

申请日：2016-09-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka SHIONOIRI ,  Shuhei NAGATSUKA ,  Hideki UOCHI

IPC: H01L29/786 ,  H01L21/78 ,  H01L21/48 ,  H01L23/31 ,  H01L23/544 ,  H01L21/66 ,  H01L23/495 ,  H01L27/12 ,  H01L21/56

CPC classification number: H01L29/78648 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/565 ,  H01L21/78 ,  H01L22/14 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49555 ,  H01L23/544 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/3262 ,  H01L29/7869 ,  H01L2223/54486 ,  H03K19/00346 ,  H05B33/0815 ,  H05B33/089

Abstract: In a logic circuit including transistors with the same conductivity, a reduction in output voltage is prevented with use of at least three transistors and a capacitor. With use of an oxide semiconductor in a semiconductor layer of the transistor, a logic circuit with high output voltage and high withstand voltage is achieved. With use of the logic circuit, a semiconductor device with high output voltage and high withstand voltage is achieved.

公开(公告)号：US20160187946A1

公开(公告)日：2016-06-30

申请号：US15059705

申请日：2016-03-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Misako MIWA ,  Yutaka SHIONOIRI

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/26 ,  G06F1/28 ,  G06F1/3203 ,  G06F1/3278 ,  G06F1/3287 ,  Y02D10/157 ,  Y02D10/171

Abstract: Provided is a power reception device in which power consumption at the time of wireless power supply is reduced. A power reception device is provided with a power reception control device capable of temporarily stopping supply of power supply voltage to a communication control unit for controlling communication in a break period of communication intermittently performed between a power transmission device and a power reception device. In the structure, a clock signal is generated on the basis of a power receiving signal transmitted from the power transmission device, and a period of communication intermittently performed can be measured using the clock signal. Further, a structure may be employed in which supply of power supply voltage to the communication unit in the power reception control device can be stopped in the break period of the communication.

公开(公告)号：US20150294693A1

公开(公告)日：2015-10-15

申请号：US14681570

申请日：2015-04-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya ONUKI ,  Kiyoshi KATO ,  Yutaka SHIONOIRI ,  Tomoaki ATSUMI ,  Takanori MATSUZAKI ,  Hiroki INOUE ,  Shuhei NAGATSUKA ,  Yuto YAKUBO

IPC: G11C5/02 ,  H01L27/12 ,  G11C5/06 ,  H01L29/24

CPC classification number: G11C5/025 ,  G11C11/4091 ,  G11C11/4097 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/24

Abstract: Provided is a semiconductor device which can achieve a reduction in its area, reduction in power consumption, and operation at a high speed. A semiconductor device 10 has a structure in which a circuit 31 including a memory circuit and a circuit 32 including an amplifier circuit are stacked. With this structure, the memory circuit and the amplifier circuit can be mounted on the semiconductor device 10 while the increase in the area of the semiconductor device 10 is suppressed. Thus, the area of the semiconductor device 10 can be reduced. Further, the circuits are formed using OS transistors, so that the memory circuit and the amplifier circuit which have low off-state current and which can operate at a high speed can be formed. Therefore, a reduction in power consumption and improvement in operation speed of the semiconductor device 10 can be achieved.

Abstract translation: 提供一种能够实现面积减小，功耗降低，高速运转的半导体装置。 半导体器件10具有堆叠包括存储电路的电路31和包括放大电路的电路32的结构。 利用这种结构，可以在半导体器件10的面积的增加被抑制的同时将存储电路和放大器电路安装在半导体器件10上。 因此，可以减小半导体器件10的面积。 此外，使用OS晶体管形成电路，从而可以形成具有低截止电流并且可以高速操作的存储电路和放大器电路。 因此，可以实现半导体器件10的功耗的降低和操作速度的提高。

公开(公告)号：US20150188435A1

公开(公告)日：2015-07-02

申请号：US14644409

申请日：2015-03-11

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yutaka SHIONOIRI ,  Junpei SUGAO

IPC: H02M3/158

CPC classification number: H02M3/158 ,  H01L27/0688 ,  H01L27/1225 ,  H02M3/073

Abstract: One object is to provide a boosting circuit whose boosting efficiency is enhanced. Another object is to provide an RFID tag including a boosting circuit whose boosting efficiency is enhanced. A node corresponding to an output terminal of a unit boosting circuit or a gate electrode of a transistor connected to the node is boosted by bootstrap operation, so that a decrease in potential which corresponds to substantially the same as the threshold potential of the transistor can be prevented and a decrease in output potential of the unit boosting circuit can be prevented.

Abstract translation: 一个目的是提供一种提升效率提高的升压电路。 另一个目的是提供一种RFID标签，其包括提升效率提高的升压电路。 与单元升压电路的输出端子或与该节点连接的晶体管的栅电极对应的节点通过自举运算来升压，使得与晶体管的阈值电位基本相同的电位降低可以是 可以防止单元升压电路的输出电位的降低。

公开(公告)号：US20130290747A1

公开(公告)日：2013-10-31

申请号：US13865418

申请日：2013-04-18

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Misako MIWA ,  Yutaka SHIONOIRI

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/28 ,  G06F1/3203 ,  G06F1/3278 ,  G06F1/3287 ,  Y02D10/157 ,  Y02D10/171

Abstract: Provided is a power reception device in which power consumption at the time of wireless power supply is reduced. A power reception device is provided with a power reception control device capable of temporarily stopping supply of power supply voltage to a communication control unit for controlling communication in a break period of communication intermittently performed between a power transmission device and a power reception device. In the structure, a clock signal is generated on the basis of a power receiving signal transmitted from the power transmission device, and a period of communication intermittently performed can be measured using the clock signal. Further, a structure may be employed in which supply of power supply voltage to the communication unit in the power reception control device can be stopped in the break period of the communication.

Abstract translation: 提供了一种在无线电力供应时的功耗降低的电力接收装置。 电力接收装置设置有能够暂时停止向在电力传输装置和电力接收装置之间间歇地进行的通信的中断期间的通信控制用的通信控制单元供给电源电压的电力接收控制装置。 在该结构中，基于从电力传输装置发送的电力接收信号生成时钟信号，并且可以使用时钟信号来测量间歇地进行的通信周期。 此外，可以采用这样的结构，其中在通信的断开期间能够停止向受电控制装置中的通信单元供电的电源电压。

公开(公告)号：US20220093452A1

公开(公告)日：2022-03-24

申请号：US17539469

申请日：2021-12-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka SHIONOIRI ,  Kosei NODA

IPC: H01L21/762 ,  H01L27/12

Abstract: An object is to provide a semiconductor device with reduced standby power. A transistor including an oxide semiconductor as an active layer is used as a switching element, and supply of a power supply voltage to a circuit in an integrated circuit is controlled by the switching element. Specifically, when the circuit is in an operation state, supply of the power supply voltage to the circuit is performed by the switching element, and when the circuit is in a stop state, supply of the power supply voltage to the circuit is stopped by the switching element. In addition, the circuit supplied with the power supply voltage includes a semiconductor element which is a minimum unit included in an integrated circuit formed using a semiconductor. Further, the semiconductor included in the semiconductor element contains silicon having crystallinity (crystalline silicon).

公开(公告)号：US20210135674A1

公开(公告)日：2021-05-06

申请号：US17150859

申请日：2021-01-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masashi FUJITA ,  Yutaka SHIONOIRI ,  Kiyoshi KATO ,  Hidetomo KOBAYASHI

IPC: H03K19/17728 ,  H03K19/173 ,  H03K19/17772 ,  H03K19/17758

Abstract: An object is to provide a semiconductor device that can maintain the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units even after supply of power supply voltage is stopped. Another object is to provide a semiconductor device in which the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units can be changed at high speed. In a reconfigurable circuit, an oxide semiconductor is used for a semiconductor element that stores data on the circuit configuration, connection relation, or the like. Specifically, the oxide semiconductor is used for a channel formation region of the semiconductor element.

公开(公告)号：US20180033807A1

公开(公告)日：2018-02-01

申请号：US15658513

申请日：2017-07-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinpei MATSUDA ,  Daigo ITO ,  Daisuke MATSUBAYASHI ,  Yasutaka SUZUKI ,  Etsuko KAMATA ,  Yutaka SHIONOIRI ,  Shuhei NAGATSUKA

IPC: H01L27/12 ,  H01L29/786 ,  H01L27/105 ,  H01L29/423

CPC classification number: H01L27/1251 ,  H01L27/1052 ,  H01L27/1225 ,  H01L27/127 ,  H01L29/42384 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A highly reliable semiconductor device capable of retaining data for a long period is provided. The transistor includes a first gate electrode, a first gate insulator over the first gate electrode, a first oxide and a second oxide over the first gate insulator, a first conductor over the first oxide, a second conductor over the second oxide, a third oxide covering the first gate insulator, the first oxide, the first conductor, the second oxide, and the second conductor, a second gate insulator over the third oxide, and a second gate electrode over the second gate insulator. An end portion of the second gate electrode is positioned between an end portion of the first conductor and an end portion of the second conductor in a channel length direction.

公开(公告)号：US20160351243A1

公开(公告)日：2016-12-01

申请号：US15160076

申请日：2016-05-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko ISHIZU ,  Shuhei NAGATSUKA ,  Tatsuya ONUKI ,  Yutaka SHIONOIRI ,  Naoaki TSUTSUI ,  Shunpei YAMAZAKI

IPC: G11C11/40 ,  H01L27/12 ,  G11C5/06 ,  G11C7/12 ,  G11C8/08 ,  H01L23/528 ,  H01L27/105 ,  G11C11/24

CPC classification number: H01L27/1207 ,  G11C5/063 ,  G11C11/401 ,  G11C11/4097 ,  G11C2029/0403 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/1255

Abstract: A memory device in which the number of films is reduced. The memory device includes a circuit and a wiring. The circuit includes a first memory cell and a second memory cell. The first memory cell includes a first transistor, a second transistor, and a first capacitor. The second memory cell includes a third transistor, a fourth transistor, and a second capacitor. The second memory cell is stacked over the first memory cell. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and the first capacitor. One of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor and the second capacitor. A gate of the first transistor and a gate of the third transistor are electrically connected to the wiring.

Abstract translation: 一种其中薄膜数量减少的存储器件。 存储器件包括电路和布线。 电路包括第一存储单元和第二存储单元。 第一存储单元包括第一晶体管，第二晶体管和第一电容器。 第二存储单元包括第三晶体管，第四晶体管和第二电容器。 第二存储单元堆叠在第一存储单元上。 第一晶体管的源极和漏极之一电连接到第二晶体管的栅极和第一电容器。 第三晶体管的源极和漏极之一电连接到第四晶体管和第二电容器的栅极。 第一晶体管的栅极和第三晶体管的栅极电连接到布线。

公开(公告)号：US20160329336A1

公开(公告)日：2016-11-10

申请号：US15145989

申请日：2016-05-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka SHIONOIRI

IPC: H01L27/108 ,  G11C11/4093 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G11C5/025 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4097 ,  G11C11/565 ,  H01L27/10814 ,  H01L27/10897 ,  H01L29/66742

Abstract: A semiconductor device includes a memory cell, a buffer circuit, a switch, first to p-th switch circuits, and first to p-th capacitors (p is an integer of 2 or more). The first to p-th switch circuits each include first to third terminals. The memory cell is electrically connected to a first electrode of the first capacitor and an input terminal of the buffer circuit through the switch. A second electrode of an i-th capacitor is electrically connected to a first terminal of an i-th switch circuit and a first electrode of an (i+1)th capacitor (i is an integer of 1 to (p-1)). A second electrode of the p-th capacitor is electrically connected to a first terminal of the p-th switch circuit. An output terminal of the buffer circuit is electrically connected to a second terminal of each of the first to p-th switch circuits. A third terminal of each of the first to p-th switch circuits is electrically connected to a wiring supplying a low-level potential.

Abstract translation: 半导体器件包括存储单元，缓冲电路，开关，第一至第p开关电路以及第一至第p电容器（p为2以上的整数）。 第一至第p开关电路各自包括第一至第三端子。 存储单元通过开关电连接到第一电容器的第一电极和缓冲电路的输入端子。 第i电容器的第二电极电连接到第i开关电路的第一端子和第（i + 1）个电容器的第一电极（i为1至（p-1）的整数） 。 第p电容器的第二电极电连接到第p开关电路的第一端子。 缓冲电路的输出端子电连接到第一至第三开关电路中的每一个的第二端子。 第一至第p开关电路中的每一个的第三端子电连接到提供低电平电位的布线。