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93 条记录 (耗时 0.046 秒)

    Method to improve reliability for flip-chip device for limiting pad design
    23.
    发明授权
    Method to improve reliability for flip-chip device for limiting pad design 有权
    提高倒装芯片器件限制焊盘设计可靠性的方法

    公开(公告)号：US06602775B1

    公开(公告)日：2003-08-05

    申请号：US09930677

    申请日：2001-08-16

    申请人： Yen-Ming Chen ,  Chia-Fu Lin ,  Kai-Ming Ching ,  Hsin-Hui Lee ,  Chao-Yuan Su ,  Li-Chi Chen

    发明人： Yen-Ming Chen ,  Chia-Fu Lin ,  Kai-Ming Ching ,  Hsin-Hui Lee ,  Chao-Yuan Su ,  Li-Chi Chen

    IPC分类号： H01L2144

    CPC分类号： H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/11912 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01059 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/05005 ,  H01L2224/05541

    摘要： A method of fabricating a solder bump including the following steps. A UBM over a substrate.having an exposed pad portion is provided. The UBM being in electrical contact with the pad portion. A first patterning layer is formed over the UBM. The first patterning layer including a photosensitive material sensitive to light having a first wavelength. A second patterning layer is formed over the first patterning layer. The second patterning layer including a photosensitive material sensitive to light having a second wavelength. The first patterning layer is selectively exposed with the light having the first wavelength, leaving a first unexposed portion substantially centered over the pad portion between first exposed portions. The second patterning layer is selectively exposed with the light having the second wavelength, leaving a second unexposed portion wider than, and substantially centered over, the first unexposed portion of the exposed first patterning layer. The second unexposed portion of the exposed second patterning layer being between exposed portions. The second unexposed portion of the exposed second patterning layer and the first unexposed portion of the exposed first patterning layer are removed to form opening. A solder plug is formed within the opening. The exposed portions of the exposed first patterning layer and the exposed portions of the exposed second patterning layer are removed. The solder plug is reflowed to form a solder bump.

    摘要翻译： 一种制造焊料凸块的方法，包括以下步骤。 提供了具有裸露焊盘部分的衬底上的UBM。 UBM与焊盘部分电接触。 在UBM上形成第一图案化层。 第一图案化层包括对具有第一波长的光敏感的感光材料。 在第一图案化层上形成第二图案化层。 第二图案化层包括对具有第二波长的光敏感的感光材料。 利用具有第一波长的光选择性地暴露第一图案化层，留下第一未曝光部分，其基本上位于第一曝光部分之间的焊盘部分的中心。 用第二波长的光选择性地暴露第二图案化层，留下第二未曝光部分比暴露的第一图案形成图案的第一未曝光部分宽且基本上居中。 曝光的第二图案化层的第二未曝光部分在曝光部分之间。 暴露的第二图案形成层的第二未曝光部分和暴露的第一图案形成层的第一未曝光部分被去除以形成开口。 在开口内形成焊塞。 暴露的第一图案形成层的暴露部分和暴露的第二图案形成层的暴露部分被去除。 焊料回流焊以形成焊料凸点。

    Semiconductor process
    25.
    发明授权
    Semiconductor process 有权
    半导体工艺

    公开(公告)号：US08647986B2

    公开(公告)日：2014-02-11

    申请号：US13220692

    申请日：2011-08-30

    申请人： Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chun-Wei Hsu ,  Yen-Ming Chen ,  Chih-Hsun Lin ,  Chang-Hung Kung

    发明人： Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chun-Wei Hsu ,  Yen-Ming Chen ,  Chih-Hsun Lin ,  Chang-Hung Kung

    IPC分类号： H01L21/306 ,  H01L21/321 ,  H01L21/3105 ,  H01L21/768

    CPC分类号： H01L21/3212 ,  H01L21/3105 ,  H01L21/31051 ,  H01L21/31053 ,  H01L21/7684 ,  H01L21/823835 ,  H01L29/665

    摘要： A semiconductor process includes the following steps. A first gate structure and a second gate structure are formed on a substrate, wherein the top of the first gate structure includes a cap layer, so that the vertical height of the first gate structure is higher than the vertical height of the second gate structure. An interdielectric layer is formed on the substrate. A first chemical mechanical polishing process is performed to expose the top surface of the cap layer. A second chemical mechanical polishing process is performed to expose the top surface of the second gate structure or an etching process is performed to remove the interdielectric layer located on the second gate structure. A second chemical mechanical polishing process is then performed to remove the cap layer.

    摘要翻译： 半导体工艺包括以下步骤。 第一栅极结构和第二栅极结构形成在基板上，其中第一栅极结构的顶部包括盖层，使得第一栅极结构的垂直高度高于第二栅极结构的垂直高度。 在基板上形成介电层。 执行第一化学机械抛光工艺以暴露盖层的顶表面。 执行第二化学机械抛光工艺以暴露第二栅极结构的顶表面，或执行蚀刻工艺以去除位于第二栅极结构上的介电层。 然后执行第二化学机械抛光工艺以除去盖层。

    Fabrication methods of integrated semiconductor structure
    26.
    发明授权
    Fabrication methods of integrated semiconductor structure 有权
    集成半导体结构的制作方法

    公开(公告)号：US08404544B1

    公开(公告)日：2013-03-26

    申请号：US13446769

    申请日：2012-04-13

    申请人： Jin-Mu Yin ,  Shyh-Wei Wang ,  Yen-Ming Chen

    发明人： Jin-Mu Yin ,  Shyh-Wei Wang ,  Yen-Ming Chen

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/28202 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4975 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78

    摘要： A method for manufacturing the integrated circuit device comprises providing a substrate having a first region, a second region, and a third region. A first gate stack, a second gate stack, and a third gate stack are formed over the substrate in the first region, the second region, and the third region, respectively. The first gate stack, the second gate stack, and the third gate stack comprise a sacrificial layer over a first dielectric layer. The first gate stack and the second gate stack are removed and a second dielectric layer is formed in the first region and the second region. The portion of second dielectric layer in the first region is transformed into a third dielectric layer by a treatment.

    摘要翻译： 一种用于制造集成电路器件的方法包括提供具有第一区域，第二区域和第三区域的衬底。 分别在第一区域，第二区域和第三区域中的衬底上形成第一栅极堆叠，第二栅极堆叠和第三栅极堆叠。 第一栅极堆叠，第二栅极堆叠和第三栅极堆叠包括在第一介电层上的牺牲层。 去除第一栅极堆叠和第二栅极堆叠，并且在第一区域和第二区域中形成第二电介质层。 通过处理将第一区域中的第二电介质层的部分转变成第三电介质层。

    Single or dual electronic package with footprint and pin sharing
    28.
    发明授权
    Single or dual electronic package with footprint and pin sharing 有权
    单或双电子封装，具有占位面积和引脚共享

    公开(公告)号：US07652893B2

    公开(公告)日：2010-01-26

    申请号：US10908122

    申请日：2005-04-28

    申请人： Yen-Ming Chen

    发明人： Yen-Ming Chen

    IPC分类号： H05K1/18

    CPC分类号： H05K1/181 ,  H05K3/3421 ,  H05K2201/09954 ,  H05K2201/10166 ,  H05K2201/10522 ,  Y02P70/611

    摘要： A 6-pin electronic package includes a first side including a pair of first outer pins and a first middle pin, and a second side including a pair of second outer pins and a second middle pin. The first outer pins and the second middle pin are operatively coupled to a first circuit to provide a first function. The second outer pins and the first middle pin are operatively coupled to a second circuit to provide a second function. The 6-pin electronic package can be replaced on a circuit substrate with a first electronic package and a second electronic package that collectively include at least six pins. The 6-pin electronic package and the first and second electronic packages can be interchangeably used on a circuit substrate of an electronic device. The circuit substrate may include any one of the 6-pin electronic package mountable to the circuit substrate, and the first and second electronic packages. The first electronic package is mountable on the circuit substrate on a same footprint as the 6-pin electronic package. The second electronic package is mountable on the circuit substrate adjacent the first electronic package such that six pins of the first and second electronic packages share the same footprint as the pins of the 6-pin electronic package.

    摘要翻译： 6引脚电子封装包括包括一对第一外部引脚和第一中间引脚的第一侧和包括一对第二外部引脚和第二中间引脚的第二侧。 第一外部引脚和第二中间引脚可操作地耦合到第一电路以提供第一功能。 第二外部引脚和第一中间引脚可操作地耦合到第二电路以提供第二功能。 6针电子封装可以在具有第一电子封装的电路基板上被替换，而第二电子封装共同包括至少六个引脚。 6针电子封装以及第一和第二电子封装可以互换地用于电子设备的电路基板上。 电路基板可以包括可安装到电路基板的6针电子封装以及第一和第二电子封装中的任何一个。 第一个电子封装以与6针电子封装相同的占位面安装在电路基板上。 第二电子封装可安装在邻近第一电子封装的电路基板上，使得第一和第二电子封装的六个引脚与6针电子封装的引脚共用相同的封装。