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公开(公告)号：US09735080B2
公开(公告)日：2017-08-15
申请号：US14876404
申请日：2015-10-06
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Shih-Chao Chiu , Chun-Hsien Lin , Yu-Cheng Pai , Wei-Chung Hsiao , Ming-Chen Sun , Tzu-Chieh Shen , Chia-Cheng Chen
IPC: H01L23/498 , H01L23/31 , H01L21/56 , H01L21/48
CPC classification number: H01L23/49861 , H01L21/4846 , H01L23/3128 , H01L23/49811 , H01L23/49827 , H01L2224/73204 , H01L2224/92125 , H01L2924/181 , H01L2924/00012
Abstract: A single-layer wiring package substrate and a method of fabricating the same are provided, the method including: forming on a carrier a wiring layer having a first surface and a second surface opposing the first surface and being in contact with the carrier; forming on the carrier and on the wiring layer a dielectric body that has a first side having a first opening, from which a portion of the wiring layer is exposed, and a second side opposing the first side and disposed at the same side as the second surface of the wiring layer; and removing the carrier, with the second side of the dielectric body and the second surface of the wiring layer exposed. Therefore, a coreless package substrate is fabricated, and the overall thickness and cost of the substrate are reduced.
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22.发明申请公开(公告)号：US20160155716A1
公开(公告)日：2016-06-02
申请号：US14837245
申请日：2015-08-27
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Ming-Chen Sun , Chun-Hsien Lin , Tzu-Chieh Shen , Shih-Chao Chiu , Yu-Cheng Pai
CPC classification number: H01L21/4853 , H01L21/486 , H01L21/563 , H01L23/3114 , H01L23/3121 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/0401 , H01L2224/13082 , H01L2224/131 , H01L2224/16238 , H01L2224/81191 , H01L2224/81815 , H01L2224/8182 , H01L2924/15313 , H05K1/111 , H05K3/20 , H05K3/205 , H05K3/428 , H05K2201/0376 , H05K2201/09481 , H05K2201/09563 , H05K2201/10674 , H01L2924/00014 , H01L2924/014
Abstract: A package substrate and a semiconductor package are provided. The package substrate includes an insulating layer having opposing first and second surfaces; a first wiring layer formed in the insulating layer, exposed from the first surface of the insulating layer, and having a plurality of first conductive pads; a second wiring layer formed in the insulating layer, exposed from the second surface, and having a plurality of second conductive pads; a third wiring layer formed on the first surface and electrically connected with the first wiring layer; a plurality of first metal bumps formed on the first conductive pads corresponding; and at least one conductive via vertically embedded in the insulating layer and electrically connected to the second and third wiring layers. Therefore, the surfaces of first conductive pads are reduced, and the non-wetting between the first conductive pads and the solder materials formed on conductive bumps is avoided.
Abstract translation: 提供封装基板和半导体封装。 封装衬底包括具有相对的第一和第二表面的绝缘层; 形成在绝缘层中的第一布线层，从绝缘层的第一表面露出并具有多个第一导电焊盘; 形成在所述绝缘层中的第二布线层，从所述第二表面露出并具有多个第二导电焊盘; 第三布线层，形成在第一表面上并与第一布线层电连接; 形成在所述第一导电焊盘上的多个第一金属凸块对应; 以及垂直嵌入绝缘层中并与第二和第三布线层电连接的至少一个导电通孔。 因此，第一导电焊盘的表面被减小，并且避免了第一导电焊盘和形成在导电凸块上的焊料材料之间的不润湿。
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公开(公告)号：US20160086879A1
公开(公告)日：2016-03-24
申请号：US14805524
申请日：2015-07-22
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Ming-Chen Sun , Chun-Hsien Lin , Tzu-Chieh Shen , Shih-Chao Chiu , Yu-Cheng Pai
IPC: H01L23/498 , H01L21/48
CPC classification number: H01L23/49827 , H01L21/4857 , H01L21/486 , H01L23/15 , H01L23/49822 , H01L2924/0002 , H05K1/0298 , H05K3/0038 , H01L2924/00
Abstract: A package substrate includes a substrate body having a first surface and a second surface opposite to the first surface; a first circuit layer formed on the first surface and having first conductive pads; a first dielectric layer formed on the first surface and the first circuit; a second circuit layer formed on the first dielectric layer and having second conductive pads; a third circuit layer formed on the second surface and having third conductive pads; a second dielectric layer formed on the second surface and the third circuit layer; a fourth circuit layer formed on the second dielectric layer and having fourth conductive pads; through holes penetrating through the first and second surfaces, and the first and second dielectric layers; and conductive vias penetrating through the through holes and electrically connected to the first, second, third and fourth conductive pads.
Abstract translation: 封装衬底包括具有第一表面和与第一表面相对的第二表面的衬底本体; 形成在第一表面上并具有第一导电焊盘的第一电路层; 形成在第一表面和第一电路上的第一电介质层; 形成在所述第一电介质层上并具有第二导电焊盘的第二电路层; 形成在所述第二表面上并具有第三导电焊盘的第三电路层; 形成在所述第二表面和所述第三电路层上的第二电介质层; 形成在所述第二电介质层上并具有第四导电焊盘的第四电路层; 穿透第一和第二表面的穿透孔以及第一和第二介电层; 以及穿过通孔并电连接到第一，第二，第三和第四导电焊盘的导电通孔。
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公开(公告)号：US09899249B2
公开(公告)日：2018-02-20
申请号：US15334569
申请日：2016-10-26
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Yu-Cheng Pai , Chun-Hsien Lin , Shih-Chao Chiu , Wei-Chung Hsiao , Ming-Chen Sun , Tzu-Chieh Shen , Chia-Cheng Chen
IPC: H01L21/683 , H05K3/40 , H01L23/498 , H01L21/48 , H05K3/46 , H05K3/20 , H01L23/00
CPC classification number: H01L21/6835 , H01L21/4857 , H01L21/486 , H01L23/498 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L24/17 , H01L2221/68345 , H01L2221/68359 , H01L2221/68381 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H05K3/20 , H05K3/4007 , H05K3/4682 , H05K2201/0367 , H05K2201/09563 , H05K2201/10674
Abstract: A coreless packaging substrate is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer, wherein the first circuit layer has a plurality of first conductive pads; a plurality of protruding elements formed on the first conductive pads, respectively, wherein each of the protruding elements has contact surfaces to be encapsulated by an external conductive element; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive vias formed in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer. The present invention strengthens the bonding between the first conductive pads and the conductive elements due to a large contact area between the protruding elements and the conductive elements.
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公开(公告)号：US20170287840A1
公开(公告)日：2017-10-05
申请号：US15621337
申请日：2017-06-13
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Yu-Cheng Pai , Wei-Chung Hsiao , Shih-Chao Chiu , Chun-Hsien Lin , Ming-Chen Sun , Tzu-Chieh Shen , Chia-Cheng Chen
IPC: H01L23/538 , H01L23/00
CPC classification number: H01L23/5389 , H01L21/568 , H01L23/3128 , H01L24/19 , H01L24/96 , H01L2224/04105 , H01L2224/16227 , H01L2224/97 , H01L2924/15311 , H01L2224/81
Abstract: A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing first and second surfaces; a plurality of first conductive pads and a plurality of second conductive pads formed on the first surface of the package body; a semiconductor component embedded in the package body and electrically connected to the first conductive pads; and a plurality of conductive elements embedded in the package body, each of the conductive elements having a first end electrically connected to a corresponding one of the second conductive pads and a second end opposing the first end and exposed from the second surface of the package body. Since the semiconductor component is embedded in the package body, the thickness of the semiconductor package structure is reduced.
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Patent Agency Ranking
公开(公告)号：US20170171981A1
公开(公告)日：2017-06-15
申请号：US15393429
申请日：2016-12-29
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chun-Hsien Lin , Shih-Chao Chiu , Yu-Cheng Pai , Tzu-Chieh Shen , Chia-Cheng Chen
CPC classification number: H05K3/007 , H05K1/0271 , H05K3/0026 , H05K3/188 , H05K3/28 , H05K3/4038 , H05K3/4682 , H05K2203/0152 , H05K2203/016 , H05K2203/1377
Abstract: The present invention provides a substrate structure and a method of fabricating the substrate structure. The method includes: forming a first wiring layer on a first carrier, forming a dielectric layer on the first wiring layer, forming a second wiring layer on the dielectric layer, forming an insulating protection layer on the second wiring layer, forming a second carrier on the insulating protection layer, and removing the first carrier. The formation of the second carrier provides the substrate structure with adequate rigidity to avoid breakage or warpage such that the miniaturization requirement can be satisfied.
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公开(公告)号：US09673140B2
公开(公告)日：2017-06-06
申请号：US14620328
申请日：2015-02-12
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chia-Cheng Chen , Ming-Chen Sun , Tzu-Chieh Shen , Shih-Chao Chiu , Wei-Chung Hsiao , Yu-Cheng Pai , Don-Son Jiang
IPC: H01L23/498 , H01L21/48 , H01L23/538 , H01L23/00 , H01L25/10 , H01L25/16
CPC classification number: H01L23/49811 , H01L21/4853 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/73 , H01L24/92 , H01L25/105 , H01L25/16 , H01L2224/131 , H01L2224/16227 , H01L2224/16235 , H01L2224/16237 , H01L2224/73204 , H01L2224/92125 , H01L2225/1023 , H01L2225/1058 , H01L2225/1076 , H01L2924/15156 , H01L2924/15159 , H01L2924/15311 , H01L2924/1579 , H01L2924/19103 , H01L2924/37001 , H01L2924/014
Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a laminate on the carrier, wherein the laminate has a built-up portion and a release portion smaller in size than the built-up portion, the release portion covering the bonding pads and the built-up portion being laminated on the release portion and the carrier; forming a plurality of conductive posts in the built-up portion; and removing the release portion and the built-up portion on the release portion such that a cavity is formed in the laminate to expose the bonding pads, the conductive posts being positioned around a periphery of the cavity. Therefore, the present invention has simplified processes.
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公开(公告)号：US09640503B2
公开(公告)日：2017-05-02
申请号：US14837245
申请日：2015-08-27
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Ming-Chen Sun , Chun-Hsien Lin , Tzu-Chieh Shen , Shih-Chao Chiu , Yu-Cheng Pai
CPC classification number: H01L21/4853 , H01L21/486 , H01L21/563 , H01L23/3114 , H01L23/3121 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/0401 , H01L2224/13082 , H01L2224/131 , H01L2224/16238 , H01L2224/81191 , H01L2224/81815 , H01L2224/8182 , H01L2924/15313 , H05K1/111 , H05K3/20 , H05K3/205 , H05K3/428 , H05K2201/0376 , H05K2201/09481 , H05K2201/09563 , H05K2201/10674 , H01L2924/00014 , H01L2924/014
Abstract: A package substrate and a semiconductor package are provided. The package substrate includes an insulating layer having opposing first and second surfaces; a first wiring layer formed in the insulating layer, exposed from the first surface of the insulating layer, and having a plurality of first conductive pads; a second wiring layer formed in the insulating layer, exposed from the second surface, and having a plurality of second conductive pads; a third wiring layer formed on the first surface and electrically connected with the first wiring layer; a plurality of first metal bumps formed on the first conductive pads corresponding; and at least one conductive via vertically embedded in the insulating layer and electrically connected to the second and third wiring layers. Therefore, the surfaces of first conductive pads are reduced, and the non-wetting between the first conductive pads and the solder materials formed on conductive bumps is avoided.
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公开(公告)号：US09510463B2
公开(公告)日：2016-11-29
申请号：US14583317
申请日：2014-12-26
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Yu-Cheng Pai , Chun-Hsien Lin , Shih-Chao Chiu , Wei-Chung Hsiao , Ming-Chen Sun , Tzu-Chieh Shen , Chia-Cheng Chen
IPC: H01L23/498 , H05K3/40 , H05K3/46 , H05K3/20
CPC classification number: H01L21/6835 , H01L21/4857 , H01L21/486 , H01L23/498 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L24/17 , H01L2221/68345 , H01L2221/68359 , H01L2221/68381 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H05K3/20 , H05K3/4007 , H05K3/4682 , H05K2201/0367 , H05K2201/09563 , H05K2201/10674
Abstract: A coreless packaging substrate is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer, wherein the first circuit layer has a plurality of first conductive pads; a plurality of protruding elements formed on the first conductive pads, respectively, wherein each of the protruding elements has contact surfaces to be encapsulated by an external conductive element; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive vias formed in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer. The present invention strengthens the bonding between the first conductive pads and the conductive elements due to a large contact area between the protruding elements and the conductive elements.
Abstract translation: 提供了一种无芯封装基板，其包括：具有相对的第一和第二表面的电介质层; 所述第一电路层嵌入在所述电介质层中并且从所述电介质层的所述第一表面露出，其中所述第一电路层具有多个第一导电焊盘; 分别形成在第一导电焊盘上的多个突起元件，其中每个突出元件具有被外部导电元件封装的接触表面; 形成在电介质层的第二表面上的第二电路层; 以及形成在电介质层中的多个导电通孔，用于电连接第一电路层和第二电路层。 本发明由于突出元件和导电元件之间的大的接触面积而增强了第一导电焊盘和导电元件之间的接合。
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公开(公告)号：US20160071780A1
公开(公告)日：2016-03-10
申请号：US14603844
申请日：2015-01-23
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Shih-Chao Chiu , Chun-Hsien Lin , Ming-Chen Sun , Yu-Cheng Pai , Tzu-Chieh Shen
IPC: H01L23/31 , H01L23/522
CPC classification number: H01L23/5226 , H01L23/3121 , H01L23/49822 , H01L23/50 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/92 , H01L25/0657 , H01L25/16 , H01L25/50 , H01L2224/131 , H01L2224/13147 , H01L2224/16145 , H01L2224/16227 , H01L2224/16235 , H01L2224/16265 , H01L2224/1703 , H01L2224/32225 , H01L2224/73253 , H01L2224/92242 , H01L2225/06513 , H01L2225/06517 , H01L2924/15153 , H01L2924/15313 , H01L2924/1579 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19103 , H01L2924/19104 , H01L2924/014
Abstract: A method of fabricating a semiconductor package is provided, including providing a carrier provided having a circuit layer and a blocking member, forming on the carrier an encapsulating layer having a first surface and a second surface opposing the first surface and encapsulating the circuit layer and the blocking member, with the first surface coupled with the carrier, and removing the carrier and the blocking member to form in the encapsulating layer via the first surface thereof an opening for an electronic component to be received therein. Before the electronic component is disposed in the opening, the circuit layer and the electronic component can be tested in advance, in order to retire the defectives. Therefore, as a defective electronic component is prevented from being disposed in the opening, no defective semiconductor package will be fabricated.
Abstract translation: 提供一种制造半导体封装的方法，包括提供具有电路层和阻挡构件的载体，在载体上形成具有第一表面和与第一表面相对的第二表面的封装层，并封装电路层和 阻挡构件，其中第一表面与载体联接，并且移除载体和阻挡构件，以在封装层中经由其第一表面形成用于待接纳在其中的电子部件的开口。 在将电子部件设置在开口内之前，可以预先测试电路层和电子部件，以便退出缺陷。 因此，由于防止有缺陷的电子元件被布置在开口中，所以不会制造有缺陷的半导体封装。
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