公开(公告)号：US20140315361A1

公开(公告)日：2014-10-23

申请号：US14325787

申请日：2014-07-08

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Seung-Chul Song

IPC: H01L21/8238

CPC classification number: H01L21/823857 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0928

Abstract: A complementary metal-oxide-semiconductor (CMOS) integrated circuit structure, and method of fabricating the same according to a replacement metal gate process. P-channel and n-channel MOS transistors are formed with high-k gate dielectric material that differ from one another in composition or thickness, and with interface dielectric material that differ from one another in composition or thickness. The described replacement gate process enables construction so that neither of the p-channel or n-channel transistor gate structures includes the metal gate material from the other transistor, thus facilitating reliable filling of the gate structures with fill metal.

公开(公告)号：US20140120668A1

公开(公告)日：2014-05-01

申请号：US14146095

申请日：2014-01-02

Applicant: Texas Instruments Incorporated

Inventor： James Joseph Chambers ,  Hiroaki Niimi

IPC: H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/3221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L27/092 ,  H01L27/11 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7833

Abstract: A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the NMOS gates such that the PMOS gates have effective work functions above 4.85 eV and the NMOS gates have effective work functions below 4.25 eV. Metal work function layers in both the NMOS and PMOS gates are oxidized to increase their effective work functions to the desired PMOS range. An oxygen diffusion blocking layer is formed over the PMOS gate and an oxygen getter is formed over the NMOS gates. A getter anneal extracts the oxygen from the NMOS work function layers and adds metal atom enrichment to the NMOS work function layers, reducing their effective work functions to the desired NMOS range. Processes and materials for the metal work function layers, the oxidation process and oxygen gettering are disclosed.

Abstract translation: 公开了一种用于在PMOS金属栅中的氧和NMOS栅极中的金属原子富集的NMOS和PMOS晶体管形成金属替代栅极的工艺，使得PMOS栅极具有高于4.85eV的有效功函数，并且NMOS栅极具有以下有效的功函数 4.25 eV。 NMOS和PMOS栅极中的金属功函数层被氧化，以将它们的有效功函数增加到期望的PMOS范围。 在PMOS栅极上形成氧扩散阻挡层，在NMOS栅极上形成氧吸气剂。 吸气剂退火从NMOS功能层提取氧气，并将金属原子富集添加到NMOS功能层，将其有效功函数降低到所需的NMOS范围。 公开了金属加工功能层的工艺和材料，氧化工艺和吸氧剂。

公开(公告)号：US10978353B2

公开(公告)日：2021-04-13

申请号：US16206045

申请日：2018-11-30

Applicant: Texas Instruments Incorporated

Inventor： Manoj Mehrotra ,  Charles Frank Machala, III ,  Rick L. Wise ,  Hiroaki Niimi

IPC: H01L21/8238 ,  H01L27/092 ,  H01L27/11 ,  H01L21/02 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20 ,  H01L29/161

Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.

公开(公告)号：US10068983B2

公开(公告)日：2018-09-04

申请号：US15222262

申请日：2016-07-28

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  James Joseph Chambers

IPC: H01L29/49 ,  H01L29/51 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285 ,  H01L29/08

Abstract: An integrated circuit containing metal replacement gates may be formed by forming a nitrogen-rich titanium-based barrier between a high-k gate dielectric layer and a metal work function layer of a PMOS transistor. The nitrogen-rich titanium-based barrier is less than 1 nanometer thick and has an atomic ratio of titanium to nitrogen of less than 43:57. The nitrogen-rich titanium-based barrier may be formed by forming a titanium based layer over the gate dielectric layer and subsequently adding nitrogen to the titanium based layer. The metal work function layer is formed over the nitrogen-rich titanium-based barrier.

公开(公告)号：US20170358659A1

公开(公告)日：2017-12-14

申请号：US15686449

申请日：2017-08-25

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Mahalingam Nandakumar

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/51 ,  H01L21/3105 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/423 ,  H01L21/32 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/28238 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/32 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66553 ,  H01L29/7833

Abstract: A replacement metal gate transistor structure and method with thin silicon nitride sidewalls and with little or no high-k dielectric on the vertical sidewalls of the replacement gate transistor trench

公开(公告)号：US09779946B2

公开(公告)日：2017-10-03

申请号：US15404561

申请日：2017-01-12

Applicant: Texas Instruments Incorporated

Inventor： Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

IPC: H01J37/00 ,  H01L21/00 ,  H01L21/28 ,  H01L21/67

CPC classification number: H01L21/28158 ,  C23C16/45557 ,  C23C16/4582 ,  H01J37/32752 ,  H01J37/32825 ,  H01J37/32899 ,  H01J2237/3321 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02326 ,  H01L21/02329 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/3105 ,  H01L21/31604 ,  H01L21/318 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/6776 ,  H01L29/42364 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/78

Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

公开(公告)号：US09576804B2

公开(公告)日：2017-02-21

申请号：US15180481

申请日：2016-06-13

Applicant: Texas Instruments Incorporated

Inventor： Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

IPC: H01J37/00 ,  H01L21/00 ,  H01L21/28 ,  H01L21/02 ,  H01L21/67 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L21/28158 ,  C23C16/45557 ,  C23C16/4582 ,  H01J37/32752 ,  H01J37/32825 ,  H01J37/32899 ,  H01J2237/3321 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02326 ,  H01L21/02329 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/3105 ,  H01L21/31604 ,  H01L21/318 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/6776 ,  H01L29/42364 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/78

Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

Abstract translation: 可以减少在制造栅极电介质结构中使用的工艺之间发生的栅极介电层的氧化物生长。 氧化物生长的减少可以通过将栅极电介质层保持在有效的方式来实现，以在制造栅极电介质结构中的至少两个顺序的工艺步骤之间减轻栅极电介质层的氧化物生长。 维持栅极电介质层在有效减少氧化物生长的环境中也改善了注入栅电介质的氮的均匀性。

公开(公告)号：US20170033018A1

公开(公告)日：2017-02-02

申请号：US15292373

申请日：2016-10-13

Applicant: Texas Instruments Incorporated

Inventor： Manoj Mehrotra ,  Charles Frank Machala, III ,  Rick L. Wise ,  Hiroaki Niimi

IPC: H01L21/8238 ,  H01L27/092 ,  H01L27/11 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L21/02 ,  H01L29/10

CPC classification number: H01L21/823807 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20

Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.

Abstract translation: 通过形成用于第一极性finFET的第一极性鳍外延层形成包含n沟道鳍FETFET和p沟道finFET的集成电路，随后形成暴露第二相反极性鳍片外延区域的硬掩模 层用于第二极性finFET。 在由硬掩模暴露的区域中形成第二极性鳍外延层。 翅片掩模限定第一极性鳍片和第二极性鳍片区域，并且随后的鳍片蚀刻形成相应的鳍片。 隔离介质材料层形成在衬底和鳍片之上。 隔离绝缘材料层被平坦化到鳍片。 隔离介电材料层是凹进的，使得翅片在隔离介电材料层之上延伸至少10纳米。 栅极电介质层和栅极形成在鳍片上。

公开(公告)号：US20160300722A1

公开(公告)日：2016-10-13

申请号：US15180481

申请日：2016-06-13

Applicant: Texas Instruments Incorporated

Inventor： Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

IPC: H01L21/28 ,  H01L29/51 ,  H01L29/49 ,  H01L21/02 ,  H01L21/67

CPC classification number: H01L21/28158 ,  C23C16/45557 ,  C23C16/4582 ,  H01J37/32752 ,  H01J37/32825 ,  H01J37/32899 ,  H01J2237/3321 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02326 ,  H01L21/02329 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/3105 ,  H01L21/31604 ,  H01L21/318 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/6776 ,  H01L29/42364 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/78

Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

Abstract translation: 可以减少在制造栅极电介质结构中使用的工艺之间发生的栅极介电层的氧化物生长。 氧化物生长的减少可以通过将栅极电介质层保持在有效的方式来实现，以在制造栅极电介质结构中的至少两个顺序的工艺步骤之间减轻栅极电介质层的氧化物生长。 维持栅极电介质层在有效减少氧化物生长的环境中也改善了注入栅电介质的氮的均匀性。

公开(公告)号：US09368355B2

公开(公告)日：2016-06-14

申请号：US14858227

申请日：2015-09-18

Applicant: Texas Instruments Incorporated

Inventor： Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

IPC: H01L21/28 ,  H01L21/316 ,  H01L21/318 ,  H01L29/51 ,  H01L29/78 ,  H01L21/02 ,  H01L21/67 ,  H01L21/3105 ,  H01L21/3205 ,  H01L21/677 ,  H01L21/324 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L21/28158 ,  C23C16/45557 ,  C23C16/4582 ,  H01J37/32752 ,  H01J37/32825 ,  H01J37/32899 ,  H01J2237/3321 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02326 ,  H01L21/02329 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/3105 ,  H01L21/31604 ,  H01L21/318 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/6776 ,  H01L29/42364 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/78

Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.