公开(公告)号：US12034074B2

公开(公告)日：2024-07-09

申请号：US17516017

申请日：2021-11-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Marie Denison ,  Sameer Pendharkar ,  Guru Mathur

IPC: H01L29/78 ,  H01L21/225 ,  H01L21/283 ,  H01L21/324 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/225 ,  H01L21/283 ,  H01L21/324 ,  H01L21/823487 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/51 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/42368 ,  H01L29/4238

Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.

公开(公告)号：US10468324B2

公开(公告)日：2019-11-05

申请号：US15183896

申请日：2016-06-16

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Marie Denison ,  Luigi Colombo ,  Sameer Pendharkar

IPC: H01L23/373 ,  H01L23/367 ,  H01L23/522 ,  H01L23/48 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528 ,  H01L21/48 ,  H01L21/02 ,  H01L23/00

Abstract: A microelectronic device includes a heat spreader layer on an electrode of a component and a metal interconnect on the heat spreader layer. The heat spreader layer is disposed above a top surface of a substrate of the semiconductor device. The heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-° K, and an electrical resistivity less than 100 micro-ohm-centimeters.

公开(公告)号：US09947784B2

公开(公告)日：2018-04-17

申请号：US15364817

申请日：2016-11-30

Applicant: Texas Instruments Incorporated

Inventor： Philip Leland Hower ,  Sameer Pendharkar ,  Marie Denison

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/36 ,  H01L21/266 ,  H01L21/324 ,  H01L21/225

CPC classification number: H01L29/7816 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/324 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain end diffused link between the buried drift region and the drain contact, and a concurrently formed channel end diffused link between the buried drift region and the channel, where the channel end diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain end diffused link.

公开(公告)号：US09793375B2

公开(公告)日：2017-10-17

申请号：US15013334

申请日：2016-02-02

Applicant: Texas Instruments Incorporated

Inventor： Philip Leland Hower ,  Sameer Pendharkar ,  Marie Denison

IPC: H01L29/66 ,  H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L21/266 ,  H01L27/088 ,  H01L21/225

CPC classification number: H01L29/66681 ,  H01L21/2253 ,  H01L21/266 ,  H01L27/088 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0642 ,  H01L29/0646 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835

Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain diffused link, a channel diffused link, and an isolation link which electrically isolated the source, where the isolation diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain diffused link.

公开(公告)号：US09355991B2

公开(公告)日：2016-05-31

申请号：US14938465

申请日：2015-11-11

Applicant: Texas Instruments Incorporated

Inventor： Marie Denison ,  Brian Ashley Carpenter ,  Osvaldo Jorge Lopez ,  Juan Alejandro Herbsommer ,  Jonathan Noquil

IPC: H01L21/50 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L23/49575 ,  H01L21/50 ,  H01L21/561 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/84 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/072 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/29101 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40145 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2924/20752

Abstract: A method for fabricating an electronic multi-output device. A substrate having a pad and pins is provided. A first chip is provided having a first and a second transistor integrated so that the first terminals of the transistors are merged into a common terminal on one chip surface and the patterned second and third terminals are on the opposite chip surface. The common first terminal is attached to the substrate pad. A driver and control chip is attached to the substrate pad adjacent to the first chip. The second terminals of the first and second transistors are connected by discrete first and second gang clips to respective substrate pins. A second chip is provided having a third and a fourth transistor integrated so that the second terminals of the transistors are merged into a common terminal on one chip surface. Patterned first and third terminals are on the opposite chip surface. The second chip is flipped to attach the first terminals vertically to the first and second gang clips. The third terminals are concurrently attached by discrete gang clips to respective pins. A common clip is attached to the common second terminal and connecting the common clip to a pin.

Abstract translation: 一种制造电子多输出装置的方法。 提供具有焊盘和引脚的基板。 提供第一芯片，其具有集成的第一和第二晶体管，使得晶体管的第一端子在一个芯片表面上合并成公共端子，并且图案化的第二和第三端子在相对的芯片表面上。 公共第一端子附接到衬底垫。 驱动器和控制芯片附接到与第一芯片相邻的衬底焊盘。 第一和第二晶体管的第二端子通过离散的第一和第二组合夹连接到相应的衬底引脚。 提供第二芯片，其具有集成的第三和第四晶体管，使得晶体管的第二端子在一个芯片表面上合并成公共端子。 图案化的第一和第三端子在相对的芯片表面上。 第二芯片被翻转以将第一终端垂直地附接到第一和第二组合夹。 第三端子通过离散的组夹同时附接到相应的引脚。 共同的夹子连接到公共第二端子并将公共夹子连接到销。

公开(公告)号：US20160064361A1

公开(公告)日：2016-03-03

申请号：US14938387

申请日：2015-11-11

Applicant: Texas Instruments Incorporated

Inventor： Marie Denison ,  Brian Ashley Carpenter ,  Osvaldo Jorge Lopez ,  Juan Alejandro Herbsommer ,  Jonathan Noquil

IPC: H01L25/065 ,  H01L23/495

CPC classification number: H01L23/49575 ,  H01L21/50 ,  H01L21/561 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/84 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/072 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/29101 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40145 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2924/20752

Abstract: An electronic multi-output device has a substrate including a first pad, a second pad and a plurality of pins. A first chip with a first transistor has a first terminal on one chip surface and a second and third terminals on the opposite chip surface. The first chip with its first terminal is tied to the first pad. A second chip with a second transistor has a first terminal on one chip surface and a second and third terminals on the opposite chip surface. The second chip with its first terminal is tied to the second pad. The second terminals are connected by a discrete first metal clip and a second metal clip to respective substrate pins. A composite third chip has a third and a fourth transistor integrated so that the first terminals of the transistors are on one chip surface. The second terminals are merged into a common terminal. The patterned third terminals are on the opposite chip surface. The first terminals are vertically attached to the first and second metal clips, respectively. The common terminal is connected by a common clip to a substrate pin.

Abstract translation: 电子多输出装置具有包括第一垫，第二垫和多个销的基板。 具有第一晶体管的第一芯片在一个芯片表面上具有第一端子，在相对的芯片表面上具有第二和第三端子。 第一个芯片与第一个终端绑在第一个焊盘上。 具有第二晶体管的第二芯片在一个芯片表面上具有第一端子，在相对的芯片表面上具有第二和第三端子。 具有第一个终端的第二个芯片与第二个焊盘相连。 第二端子通过离散的第一金属夹和第二金属夹连接到相应的衬底引脚。 复合第三芯片具有集成的晶体管的第一端子在一个芯片表面上的第三和第四晶体管。 第二个终端被合并成一个公共终端。 图案化的第三端子在相对的芯片表面上。 第一端子分别垂直地附接到第一和第二金属夹。 公共端子通过公共夹子连接到基板引脚。

公开(公告)号：US09240446B2

公开(公告)日：2016-01-19

申请号：US14807276

申请日：2015-07-23

Applicant: Texas Instruments Incorporated

Inventor： Guru Mathur ,  Marie Denison ,  Sameer Pendharkar

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L29/10 ,  H01L21/266

CPC classification number: H01L29/063 ,  H01L21/266 ,  H01L21/76232 ,  H01L21/823418 ,  H01L21/823456 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813

Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define at least one vertical drift region bounded on at least two opposite sides by the deep trench structures. The deep trench structures include dielectric liners. The deep trench structures are spaced so as to form RESURF regions for the drift region. Vertical gates are formed in vertically oriented gate trenches in the dielectric liners of the deep trench structures, abutting the vertical drift regions. A body implant mask for implanting dopants for the transistor body is also used as an etch mask for forming the vertically oriented gate trenches in the dielectric liners.

公开(公告)号：US09214415B2

公开(公告)日：2015-12-15

申请号：US14181966

申请日：2014-02-17

Applicant: Texas Instruments Incorporated

Inventor： Marie Denison ,  Brian Ashley Carpenter ,  Osvaldo Jorge Lopez ,  Juan Alejandro Herbsommer ,  Jonathan Noquil

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/49575 ,  H01L21/50 ,  H01L21/561 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/84 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/072 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/29101 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40145 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2924/20752

Abstract: A packaged multi-output converter (200) comprising a leadframe with a chip pad (201) as ground terminal and a plurality of leads (202) including the electrical input terminal (203); a first FET chip (sync chip, 220) with its source terminal affixed to the leadframe and on its opposite surface a first drain terminal (221) positioned adjacent to a second drain terminal (222), the drain terminals connected respectively by a first (241) and a second (242) metal clip to a first (204) and second (205) output lead; a second FET chip (control chip, 211), positioned vertically over the first drain terminal, with its source terminal attached onto the first clip; a third FET chip (control chip, 212), positioned vertically over the second drain terminal, with its source terminal attached onto the second clip; and the drain terminals (213, 214) of the second and third chips attached onto a third metal clip (260) connected to the input lead (203).

Abstract translation: 一种封装的多输出转换器（200），包括具有作为接地端子的芯片焊盘（201）的引线框和包括所述电输入端子（203）的多个引线（202）; 第一FET芯片（同步芯片，220），其源极端子固定到引线框架，并且在其相对表面上与第二漏极端子（222）相邻定位的第一漏极端子（221），漏极端子分别由第一（ 241）和第二（242）金属夹到第一（204）和第二（205）输出引线; 位于第一漏极端子上方的第二FET芯片（控制芯片211），其源极端子附接到第一夹子上; 第三FET芯片（控制芯片212），其垂直地位于第二漏极端子上，其源极端子附接到第二夹子上; 和连接到连接到输入引线（203）的第三金属夹（260）上的第二和第三芯片的漏极端子（213,214）。

公开(公告)号：US20140306332A1

公开(公告)日：2014-10-16

申请号：US14181966

申请日：2014-02-17

Applicant: Texas Instruments Incorporated

Inventor： Marie Denison ,  Brian Ashley Carpenter ,  Osvaldo Jorge Lopez ,  Juan Alejandro Herbsommer ,  Jonathan Noquil

IPC: H01L23/495 ,  H01L21/50 ,  H01L23/48

CPC classification number: H01L23/49575 ,  H01L21/50 ,  H01L21/561 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/84 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/072 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/29101 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40145 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2924/20752

Abstract: A packaged multi-output converter (200) comprising a leadframe with a chip pad (201) as ground terminal and a plurality of leads (202) including the electrical input terminal (203); a first FET chip (sync chip, 220) with its source terminal affixed to the leadframe and on its opposite surface a first drain terminal (221) positioned adjacent to a second drain terminal (222), the drain terminals connected respectively by a first (241) and a second (242) metal clip to a first (204) and second (205) output lead; a second FET chip (control chip, 211), positioned vertically over the first drain terminal, with its source terminal attached onto the first clip; a third FET chip (control chip, 212), positioned vertically over the second drain terminal, with its source terminal attached onto the second clip; and the drain terminals (213, 214) of the second and third chips attached onto a third metal clip (260) connected to the input lead (203).

Abstract translation: 一种封装的多输出转换器（200），包括具有作为接地端子的芯片焊盘（201）的引线框和包括所述电输入端子（203）的多个引线（202）; 第一FET芯片（同步芯片，220），其源极端子固定到引线框架，并且在其相对表面上与第二漏极端子（222）相邻定位的第一漏极端子（221），漏极端子分别由第一（ 241）和第二（242）金属夹到第一（204）和第二（205）输出引线; 位于第一漏极端子上方的第二FET芯片（控制芯片211），其源极端子附接到第一夹子上; 第三FET芯片（控制芯片212），其垂直地位于第二漏极端子上，其源极端子附接到第二夹子上; 和连接到连接到输入引线（203）的第三金属夹（260）上的第二和第三芯片的漏极端子（213,214）。

公开(公告)号：US08766359B2

公开(公告)日：2014-07-01

申请号：US14073472

申请日：2013-11-06

Applicant: Texas Instruments Incorporated

Inventor： Marie Denison ,  Sameer Pendharkar

IPC: H01L29/78

CPC classification number: H01L29/7816 ,  H01L21/76224 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0882 ,  H01L29/4236 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: An integrated circuit containing an extended drain MOS transistor with deep semiconductor (SC) RESURF trenches in the drift region, in which each deep SC RESURF trench has a semiconductor RESURF layer at a sidewall of the trench contacting the drift region. The semiconductor RESURF layer has an opposite conductivity type from the drift region. The deep SC RESURF trenches have depth:width ratios of at least 5:1, and do not extend through a bottom surface of the drift region. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching undersized trenches and counterdoping the sidewall region to form the semiconductor RESURF layer. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching trenches and growing an epitaxial layer on the sidewall region to form the semiconductor RESURF layer.

Abstract translation: 一种集成电路，其包含在漂移区域中具有深半导体（SC）RESURF沟槽的扩展漏极MOS晶体管，其中每个深的SC RESURF沟槽在与漂移区接触的沟槽的侧壁处具有半导体RESURF层。 半导体RESURF层具有与漂移区相反的导电类型。 深的SC RESURF沟槽具有至少5：1的深度：宽度比，并且不延伸穿过漂移区域的底部表面。 通过蚀刻尺寸不足的沟槽和反向掺杂侧壁区以形成半导体RESURF层，在漂移区中形成具有深SC RESURF沟槽的集成电路的工艺。 通过蚀刻沟槽并在侧壁区域上生长外延层以形成半导体RESURF层，在漂移区中形成具有深SC RESURF沟槽的集成电路的工艺。