公开(公告)号：US20230031204A1

公开(公告)日：2023-02-02

申请号：US17963149

申请日：2022-10-10

Applicant: Texas Instruments Incorporated

Inventor： Klaas De Haan ,  Mikhail Valeryevich Ivanov ,  Tobias Bernhard Fritz ,  Swaminathan Sankaran ,  Thomas Dyer Bonifield

IPC: H01L23/522 ,  H01L21/50 ,  H04L25/02 ,  H01L23/50

Abstract: An electronic device has a substrate and first and second metallization levels with a resonant circuit. The first metallization level has a first dielectric layer on a side of the substrate, and a first metal layer on the first dielectric layer. The second metallization level has a second dielectric layer on the first dielectric layer and the first metal layer, and a second metal layer on the second dielectric layer. The electronic device includes a first plate in the first metal layer, and a second plate spaced apart from the first plate in the second metal layer to form a capacitor. The electronic device includes a winding in one of the first or second metal layers and coupled to one of the first or second plates in a resonant circuit.

公开(公告)号：US20220244320A1

公开(公告)日：2022-08-04

申请号：US17512382

申请日：2021-10-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Thomas Dyer Bonifield

IPC: G01R31/52 ,  G01R31/14

Abstract: A method includes applying an AC test voltage signal to a terminal of an electronic device, the AC test voltage signal having a test frequency of 100 Hz or more, sensing a current signal of the electronic device during application of the AC test voltage signal, and identifying the electronic device as passing an isolation test in response to the current signal being less than a current threshold. After identifying the electronic device as passing the isolation test, the method includes applying a second AC test voltage signal to the terminal of the electronic device, the second AC test voltage signal having a second test frequency of 100 Hz or more, measuring a partial discharge of the electronic device during application of the second AC test voltage signal, and identifying the electronic device as passing a partial discharge test in response to the partial discharge being less than a threshold.

公开(公告)号：US11251138B2

公开(公告)日：2022-02-15

申请号：US16717262

申请日：2019-12-17

Applicant: Texas Instruments Incorporated

Inventor： Scott Robert Summerfelt ,  Thomas Dyer Bonifield ,  Sreeram Subramanyam Nasum ,  Peter Smeys ,  Benjamin Stassen Cook

IPC: H01L23/00 ,  H01L23/29 ,  H01L21/78 ,  H01L23/64 ,  H01L21/762 ,  H01L23/31

Abstract: In described examples of an integrated circuit (IC) there is a substrate of semiconductor material having a first region with a first transistor formed therein and a second region with a second transistor formed therein. An isolation trench extends through the substrate and separates the first region of the substrate from the second region of the substrate. An interconnect region having layers of dielectric is disposed on a top surface of the substrate. A dielectric polymer is disposed in the isolation trench and in a layer over the backside surface of the substrate. An edge of the polymer layer is separated from the perimeter edge of the substrate by a space.

公开(公告)号：US10998278B2

公开(公告)日：2021-05-04

申请号：US16832356

申请日：2020-03-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey Alan West ,  Thomas Dyer Bonifield ,  Yoshihiro Takei ,  Mitsuhiro Sugimoto

IPC: H01L23/64 ,  H01L25/18

Abstract: A microelectronic device contains a high voltage component having an upper plate and a lower plate. The upper plate is isolated from the lower plate by a main dielectric between the upper plate and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the upper plate and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer of silicon nitride having a refractive index between 2.11 and 2.23. The lower-bandgap dielectric layer extends beyond the upper plate continuously around the upper plate. The lower-bandgap dielectric layer has an isolation break surrounding the upper plate at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the upper plate.

公开(公告)号：US10580722B1

公开(公告)日：2020-03-03

申请号：US16134924

申请日：2018-09-18

Applicant: Texas Instruments Incorporated

Inventor： Anindya Poddar ,  Thomas Dyer Bonifield ,  Woochan Kim ,  Vivek Kishorechand Arora

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/62 ,  H01L29/00 ,  H01L23/552 ,  H01L23/544 ,  H01L23/495 ,  H01L23/532

Abstract: Described herein is a technology or a method for fabricating a flip-chip on lead (FOL) semiconductor package. A lead frame includes an edge on surface that has a geometric shape that provides a radial and uniform distribution of electric fields. By placing the formed geometric shape along an active die of a semiconductor chip, the electric fields that are present in between the lead frame and the semiconductor chip are uniformly concentrated.

公开(公告)号：US09893008B2

公开(公告)日：2018-02-13

申请号：US15193355

申请日：2016-06-27

Applicant: Texas Instruments Incorporated

Inventor： Thomas Dyer Bonifield ,  Byron Williams ,  Shrinivasan Jaganathan ,  David Larkin ,  Dhaval Atul Saraiya

IPC: H05K1/09 ,  H01L23/522 ,  H05K1/03 ,  H05K1/16 ,  H01L23/62 ,  H05K1/02 ,  H05K3/46 ,  H05K3/00 ,  H05K1/11 ,  H01L23/498 ,  H01L23/528 ,  H01L23/532 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L23/5223 ,  H01L23/49811 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/538 ,  H01L23/62 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02166 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48463 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49177 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/14335 ,  H05K1/0256 ,  H05K1/0257 ,  H05K1/0262 ,  H05K1/0306 ,  H05K1/0346 ,  H05K1/09 ,  H05K1/112 ,  H05K1/162 ,  H05K1/165 ,  H05K3/0088 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/0175 ,  H05K2201/0191 ,  H05K2201/0195 ,  H05K2201/0746 ,  H05K2201/09409 ,  H05K2201/0949 ,  H05K2201/09672 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels. The first metal level is separated from the monolithic substrate by an inorganic PMD layer. The second metal level is separated from the first metal level by a layer of silicon dioxide. The third metal level is separated from the second metal level by at least 20 microns of polyimide or PBO. The isolation components include bondpads on the third metal level for connections to other devices. A dielectric layer is formed over the third metal level, exposing the bondpads. The isolation device contains no transistors.

公开(公告)号：US20170343622A1

公开(公告)日：2017-11-30

申请号：US15169639

申请日：2016-05-31

Applicant: Texas Instruments Incorporated

Inventor： Erika Lynn Mazotti ,  Dok Won Lee ,  William David French ,  Byron J R Shulver ,  Thomas Dyer Bonifield ,  Ricky Alan Jackson ,  Neil Gibson

IPC: G01R33/04 ,  G01R33/00

CPC classification number: G01R33/04 ,  G01R33/0052

Abstract: An integrated fluxgate device has a magnetic core on a control circuit. The magnetic core has a volume and internal structure sufficient to have low magnetic noise and low non-linearity. A stress control structure is disposed proximate to the magnetic core. An excitation winding, a sense winding and a compensation winding are disposed around the magnetic core. An excitation circuit disposed in the control circuit is coupled to the excitation winding, configured to provide current at high frequency to the excitation winding sufficient to generate a saturating magnetic field in the magnetic core during each cycle at the high frequency. An isolation structure is disposed between the magnetic core and the windings, sufficient to enable operation of the excitation winding and the sense winding at the high frequency at low power.

公开(公告)号：US09408302B2

公开(公告)日：2016-08-02

申请号：US14643230

申请日：2015-03-10

Applicant: Texas Instruments Incorporated

Inventor： Thomas Dyer Bonifield ,  Byron Williams ,  Shrinivasan Jaganathan ,  David Larkin ,  Dhaval Atul Saraiya

IPC: H05K1/09 ,  H05K1/03 ,  H05K1/16 ,  H01L23/62 ,  H05K1/02 ,  H05K3/46 ,  H05K3/00 ,  H05K1/11

CPC classification number: H01L23/5223 ,  H01L23/49811 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/538 ,  H01L23/62 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02166 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48463 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49177 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/14335 ,  H05K1/0256 ,  H05K1/0257 ,  H05K1/0262 ,  H05K1/0306 ,  H05K1/0346 ,  H05K1/09 ,  H05K1/112 ,  H05K1/162 ,  H05K1/165 ,  H05K3/0088 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/0175 ,  H05K2201/0191 ,  H05K2201/0195 ,  H05K2201/0746 ,  H05K2201/09409 ,  H05K2201/0949 ,  H05K2201/09672 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels. The first metal level is separated from the monolithic substrate by an inorganic PMD layer. The second metal level is separated from the first metal level by a layer of silicon dioxide. The third metal level is separated from the second metal level by at least 20 microns of polyimide or PBO. The isolation components include bondpads on the third metal level for connections to other devices. A dielectric layer is formed over the third metal level, exposing the bondpads. The isolation device contains no transistors.

公开(公告)号：US12230669B2

公开(公告)日：2025-02-18

申请号：US18242717

申请日：2023-09-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Thomas Dyer Bonifield ,  Jeffrey Alan West ,  Byron Lovell Williams ,  Elizabeth Costner Stewart

IPC: H01L23/522 ,  H01L27/02 ,  H01L49/02

Abstract: A galvanic isolation capacitor device includes a semiconductor substrate and a PMD layer over the semiconductor substrate. The PMD layer has a first thickness. A lower metal plate is over the PMD layer and an ILD layer is on the lower metal plate; the ILD layer has a second thickness. A ratio of the first thickness to the second thickness is between about 1 and 1.55 inclusive. A first upper metal plate over the ILD layer has a first area and a second upper metal plate over the ILD layer has a second area; a ratio of the first area to the second area is greater than about 5. The galvanic isolation capacitor device can be part of a multi-chip module.

公开(公告)号：US20240113155A1

公开(公告)日：2024-04-04

申请号：US18146591

申请日：2022-12-27

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Hung-Yu Chou ,  Byron Lovell Williams ,  Thomas Dyer Bonifield

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/16

CPC classification number: H01L28/10 ,  H01L21/565 ,  H01L23/3121 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/167 ,  H01L2224/45147 ,  H01L2224/45664 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48195 ,  H01L2224/48245 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/4903 ,  H01L2224/49052 ,  H01L2224/49109 ,  H01L2924/1461 ,  H01L2924/3862

Abstract: A microelectronic device includes a galvanic isolation component having a lower isolation element over a substrate with lower bond pads connected to the lower isolation element, a dielectric plateau over the lower isolation element that does not extend to the lower bond pads, and an upper isolation element and upper bond pads over the dielectric plateau. The upper bond pads are laterally separated from the lower bond pads by an isolation distance. The microelectronic device includes high voltage wire bonds on the upper bond pads that extend upward, within 10 degrees of vertical, for a vertical distance greater than the isolation distance. The microelectronic device further includes low voltage wire bonds on the lower bond pads that have a loop height directly over a perimeter of the substrate that is less than 5 times a wire diameter of the low voltage wire bonds.