公开(公告)号：US20090166739A1

公开(公告)日：2009-07-02

申请号：US12085776

申请日：2006-11-30

申请人： Tadahiro Ohmi ,  Akinobu Teramoto

发明人： Tadahiro Ohmi ,  Akinobu Teramoto

IPC分类号： H01L27/092

CPC分类号： H01L27/1211 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/845 ,  H01L29/045 ,  H01L29/785 ,  H01L2029/7857

摘要： In order to obtain substantially the same operating speed of a p-type MOS transistor and an n-type MOS transistor forming a CMOS circuit, the n-type MOS transistor has a three-dimensional structure having a channel region on both the (100) plane and the (110) plane and the p-type MOS transistor has a planar structure having a channel region only on the (110) plane. Further, both the transistors are substantially equal to each other in the areas of the channel regions and gate insulating films. Accordingly, it is possible to make the areas of the gate insulating films and so on equal to each other and also to make the gate capacitances equal to each other.

摘要翻译： 为了获得形成CMOS电路的p型MOS晶体管和n型MOS晶体管的大致相同的工作速度，n型MOS晶体管具有三维结构，在（100） （110）面和p型MOS晶体管具有仅在（110）面上具有沟道区的平面结构。 此外，两个晶体管在沟道区域和栅极绝缘膜的区域中基本上彼此相等。 因此，可以使栅极绝缘膜等的面积相等并且使栅极电容彼此相等。

公开(公告)号：US20090104787A1

公开(公告)日：2009-04-23

申请号：US11917013

申请日：2006-06-07

申请人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Minoru Honda ,  Toshio Nakanishi

发明人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Minoru Honda ,  Toshio Nakanishi

IPC分类号： H01L21/31 ,  G05B19/00 ,  C23C16/34

CPC分类号： H01L21/3185

摘要： A nitriding process is performed at a process temperature of 500° C. or more by causing microwave-excited high-density plasma of a nitrogen-containing gas to act on silicon in the surface of a target object, inside a process container of a plasma processing apparatus. The plasma is generated by supplying microwaves into the process container from a planar antenna having a plurality of slots.

摘要翻译： 通过使含氮气体的微波激发的高密度等离子体作用在目标物体的表面的硅上，等离子体的处理容器内，在500℃以上的过程温度下进行氮化处理 处理装置。 通过从具有多个槽的平面天线向处理容器提供微波产生等离子体。

公开(公告)号：US20080135954A1

公开(公告)日：2008-06-12

申请号：US11812807

申请日：2007-06-21

申请人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Koutaro Tanaka

发明人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Koutaro Tanaka

IPC分类号： H01L29/78 ,  H01L21/3205

CPC分类号： H01L29/7802 ,  H01J37/32192 ,  H01L21/049 ,  H01L29/1608 ,  H01L29/518 ,  H01L29/6606 ,  H01L29/66068

摘要： A film with small hysteresis and high voltage resistance is obtained by reducing the carbon content in a gate insulating film on a SiC substrate. Specifically, the carbon content in the gate insulating film is set to 1×1020 atoms/cm3 or less. For this, using a plasma processing apparatus, a silicon oxide film is formed on the SiC substrate and then the formed silicon oxide film is reformed by exposure to radicals containing nitrogen atoms. Thus, the gate insulating film excellent in electrical properties is obtained.

摘要翻译： 通过降低SiC衬底上的栅极绝缘膜中的碳含量，获得具有小滞后和高耐电压性的膜。 具体地，将栅极绝缘膜中的碳含量设定为1×10 20原子/ cm 3以下。 为此，使用等离子体处理装置，在SiC衬底上形成氧化硅膜，然后通过暴露于含有氮原子的基团将形成的氧化硅膜重整。 因此，获得了电性能优异的栅极绝缘膜。

公开(公告)号：US20070105523A1

公开(公告)日：2007-05-10

申请号：US10560703

申请日：2004-06-11

申请人： Takefumi Nishimuta ,  Hiroshi Miyagi ,  Tadahiro Ohmi ,  Shigetoshi Sugawa ,  Akinobu Teramoto

发明人： Takefumi Nishimuta ,  Hiroshi Miyagi ,  Tadahiro Ohmi ,  Shigetoshi Sugawa ,  Akinobu Teramoto

IPC分类号： H04B1/10 ,  H04B1/28 ,  H04B1/16

CPC分类号： H01L21/82385 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/785 ,  H03F1/26 ,  H03F2200/372 ,  H03G1/0029 ,  H03G1/007

摘要： A low noise amplifier is assumed to comprise an MIS transistor and to amplify an input signal keeping noise at a low level, and the MIS transistor comprises a semiconductor substrate for comprising a first crystal plane as a principal plane, a semiconductor structure, formed as a part of the semiconductor substrate, for comprising a pair of sidewall planes defined by the second crystal plane different from the first crystal plane and a top plane defined by the third crystal plane different from the second crystal plane, a gate insulator of uniform thickness covering the principal plane, the sidewall planes and the top plane, a gate electrode for continuously covering the principal plane, the sidewall planes and the top plane on top of the gate insulator, and a single conductivity type diffusion area formed in the region to either side of the gate electrode in the semiconductor substrate and the semiconductor structure and continuously extending along the principal plane, the sidewall planes and the top plane. Such a configuration allows significant reduction of the 1/f noise and the signal distortion applied to an output signal by the low noise amplifier and therefore a circuit for compensating for the reduction of the amplitude is no longer of necessity, allowing reduction in size.

摘要翻译： 假设低噪声放大器包括MIS晶体管并且将保持噪声保持在低电平的输入信号放大，并且MIS晶体管包括用于包括第一晶面作为主平面的半导体衬底，形成为 所述半导体衬底的一部分包括由不同于所述第一晶体面的所述第二晶体面限定的一对侧壁平面和由与所述第二晶体面不同的所述第三晶体面限定的顶面，覆盖所述半导体衬底的均匀厚度的栅极绝缘体 主平面，侧壁平面和顶面，用于连续覆盖主平面，侧壁平面和栅极绝缘体顶部的顶面的栅极，以及在该区域中形成的单一导电型扩散区域 半导体衬底中的栅电极和半导体结构，并且沿着主平面连续延伸，侧壁p 车道和顶层飞机。 这样的配置允许显着降低由低噪声放大器施加到输出信号的1 / f噪声和信号失真，因此不再需要用于补偿幅度减小的电路，从而允许尺寸减小。

公开(公告)号：US20060216948A1

公开(公告)日：2006-09-28

申请号：US10547504

申请日：2004-03-04

申请人： Tadahiro Ohmi ,  Akinobu Teramoto

发明人： Tadahiro Ohmi ,  Akinobu Teramoto

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02052 ,  H01L21/67017 ,  H01L21/67028 ,  H01L21/67034 ,  H01L21/6704 ,  H01L21/67046 ,  H01L21/67051 ,  H01L21/6715 ,  H01L21/67161 ,  H01L21/67173

摘要： An object of the present invention is to completely remove water adhering to a substrate due to cleaning and carry the substrate with the water being removed, to a film forming unit. The present invention is a substrate processing system including: a cleaning unit for cleaning a substrate with a cleaning solution; a water removing unit for removing water adhering to the substrate cleaned in the cleaning unit; and a carrier section for carrying the substrate from which water has been removed in the water removing unit to another substrate processing unit through a dry atmosphere.

摘要翻译： 本发明的一个目的是完全去除由于清洗而附着在基材上的水，并且将被除去的水携带在基板上的成膜单元。 本发明是一种基板处理系统，包括：用清洗液清洗基板的清洗单元; 除水单元，用于去除在清洁单元中清洁的粘附到基底上的水; 以及承载部，其通过干燥气氛将去除水分中的水从基板移出到另一基板处理单元。

公开(公告)号：US20060180840A1

公开(公告)日：2006-08-17

申请号：US10560397

申请日：2004-06-11

申请人： Takefumi Nishimuta ,  Hiroshi Miyagi ,  Tadahiro Ohmi ,  Shigetoshi Sugawa ,  Akinobu Teramoto

发明人： Takefumi Nishimuta ,  Hiroshi Miyagi ,  Tadahiro Ohmi ,  Shigetoshi Sugawa ,  Akinobu Teramoto

IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L29/66787 ,  H01L21/823807 ,  H01L21/82385 ,  H01L27/092

摘要： A rectangular parallelepiped projecting portion (21) having a height of HB and a width of WB is formed on a silicon substrate, and a gate oxide film is formed on a part of the top surface and the side surface of the projecting portion (21), thereby generating a MOS transistor. By connecting in parallel a p-channel MOS transistor and an n-channel MOS transistor produced as described above, a switch of a switched capacitor circuit is configured, thereby reducing a leak current and a DC offset of the switched capacitor circuit.

摘要翻译： 在硅衬底上形成具有H B高度和W B B的宽度的长方体的突出部分（21），并且栅极氧化膜形成在 突出部分（21）的顶表面和侧表面的一部分，从而产生MOS晶体管。 通过并联连接如上所述制造的p沟道MOS晶体管和n沟道MOS晶体管，构造开关电容器电路的开关，从而减小开关电容器电路的漏电流和DC偏移。

公开(公告)号：US08895410B2

公开(公告)日：2014-11-25

申请号：US11991908

申请日：2005-09-13

申请人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Hiroshi Akahori

发明人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Hiroshi Akahori

IPC分类号： H01L21/322 ,  H01L21/223 ,  H01L21/30 ,  H01L29/78 ,  H01L29/66 ,  H01L21/31

CPC分类号： H01L21/3003 ,  B65G2201/0247 ,  H01L21/31 ,  H01L29/6659 ,  H01L29/7833

摘要： A cause of deteriorating the hydrogen termination on the surface of a wafer is found to be water adsorbed on the surface. By exposing the wafer to an inert gas atmosphere containing an H2 gas so as to suppress the oxidation reaction due to the water, it is possible to improve the hydrogen termination on the wafer surface.

摘要翻译： 发现晶片表面的氢终止劣化的原因是水被吸附在表面上。 通过将晶片暴露于含有H 2气体的惰性气体气氛中以抑制由于水引起的氧化反应，可以改善晶片表面上的氢终止。

公开(公告)号：US08643106B2

公开(公告)日：2014-02-04

申请号：US12308846

申请日：2007-06-21

申请人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Cheng Weitao

发明人： Tadahiro Ohmi ,  Akinobu Teramoto ,  Cheng Weitao

IPC分类号： H01L27/12

CPC分类号： H01L29/78654 ,  H01L29/78603 ,  H01L29/78648

摘要： A transistor capable of adjusting a threshold value is obtained by adjusting an impurity concentration of a silicon substrate supporting an SOI layer and by controlling a thickness of a buried insulating layer formed on a surface of the silicon substrate in contact with the SOI layer.

摘要翻译： 通过调整支撑SOI层的硅衬底的杂质浓度，并且通过控制形成在与SOI层接触的硅衬底表面上的掩埋绝缘层的厚度来获得能够调节阈值的晶体管。

公开(公告)号：US08633395B2

公开(公告)日：2014-01-21

申请号：US12995514

申请日：2009-05-22

申请人： Tadahiro Ohmi ,  Shigetoshi Sugawa ,  Hiroshi Imai ,  Akinobu Teramoto

发明人： Tadahiro Ohmi ,  Shigetoshi Sugawa ,  Hiroshi Imai ,  Akinobu Teramoto

IPC分类号： H05K1/03 ,  H05K1/11

CPC分类号： H05K1/0218 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2223/6688 ,  H01L2924/0002 ,  H01L2924/19032 ,  H01L2924/3011 ,  H05K1/025 ,  H05K1/0265 ,  H05K3/4652 ,  H05K2201/0191 ,  H05K2201/0352 ,  H05K2201/0715 ,  H05K2201/096 ,  H05K2201/09618 ,  H05K2201/09727 ,  H05K2201/09972 ,  H01L2924/00

摘要： A multilayer wiring board 100 comprises a first wiring region 101 where wirings 103a and insulating layers 104a and 104b are alternately laminated, and a second wiring region 102 where a thickness H2 of an insulating layer 104 is twice or more a thickness H1 of the insulating layer in the first wiring region 101 and a width W2 of a wiring 103b is twice or more a width W1 of the wiring in the first wiring region 101. The first wiring region 101 and the second wiring region 102 are integrally formed on the same board.

摘要翻译： 多层布线基板100包括：布线103a和绝缘层104a，104b交替层叠的第一布线区域101和绝缘层104的厚度H2为绝缘层的厚度H1的两倍以上的第二布线区域102 在第一布线区域101中，布线103b的宽度W2是第一布线区域101中的布线的宽度W1的两倍或更多倍。第一布线区域101和第二布线区域102一体地形成在同一个板上。

公开(公告)号：US20130292700A1

公开(公告)日：2013-11-07

申请号：US13981048

申请日：2012-01-23

申请人： Akinobu Teramoto ,  Hiroshi Kambayashi ,  Hirokazu Ueda ,  Yuichiro Morozumi ,  Katsushige Harada ,  Kazuhide Hasebe ,  Tadahiro Ohmi

发明人： Akinobu Teramoto ,  Hiroshi Kambayashi ,  Hirokazu Ueda ,  Yuichiro Morozumi ,  Katsushige Harada ,  Kazuhide Hasebe ,  Tadahiro Ohmi

IPC分类号： H01L29/20 ,  H01L21/02

CPC分类号： H01L21/02274 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/0254 ,  H01L21/28264 ,  H01L23/564 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42364 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a semiconductor device including GaN (gallium nitride) that composes a semiconductor layer and includes forming a gate insulating film, in which at least one film selected from the group of a SiO2 film and an Al2O3 film is formed on a nitride layer containing GaN by using microwave plasma and the formed film is used as at least a part of the gate insulating film.

摘要翻译： 一种制造半导体器件的方法，该半导体器件包括构成半导体层并包括形成栅极绝缘膜的GaN（氮化镓），其中在氮化物层上形成选自SiO 2膜和Al 2 O 3膜中的至少一种膜 通过使用微波等离子体形成含GaN的GaN，并且将形成的膜用作栅极绝缘膜的至少一部分。