公开(公告)号：US20070151845A1

公开(公告)日：2007-07-05

申请号：US11430948

申请日：2006-05-10

Applicant: Chieh-Kai Chang ,  Chao-Kai Cheng ,  Ming-Huan Yang ,  Chung-Wei Wang ,  Fu-Kang Cheng ,  Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Chih-Ming Chang ,  Cheng-Po Yu

Inventor： Chieh-Kai Chang ,  Chao-Kai Cheng ,  Ming-Huan Yang ,  Chung-Wei Wang ,  Fu-Kang Cheng ,  Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Chih-Ming Chang ,  Cheng-Po Yu

IPC: C25C7/00

CPC classification number: C25D17/00 ,  C25D5/003 ,  C25D5/08 ,  C25D17/004 ,  C25D17/02 ,  C25D21/12 ,  H05K3/423 ,  H05K2203/074 ,  H05K2203/1518

Abstract: An apparatus for metal plating on a substrate with through-holes includes a chamber that the substrate is disposed inside the chamber to be divided into two sections. A pressure generator and a pressure controller are connected to this and correspond to two sides of the substrate respectively. The pressure generator is used for pumping a electrolyte flowed parallel to the surface of the substrate into the chamber. The pressure controller is used for channeling the electrolyte off the chamber and controlling the pressure differences between the two sides of the substrate. So that the electrolyte flowed parallel to the surface of the substrate is pumped by the pressure generator and it passes several through-holes to control the thickness of metal plating on the.substrate and inner walls of the through-holes.

Abstract translation: 用于在具有通孔的基板上进行金属电镀的设备包括：室，其设置在室内，以分成两部分。 压力发生器和压力控制器分别连接到基板的两侧。 压力发生器用于将平行于衬底的表面流动的电解质泵入室中。 压力控制器用于将电解质引出室，并控制衬底两侧之间的压力差。 使得平行于基板表面流动的电解质被压力发生器泵送，并且通过几个通孔以控制通孔的内壁和内壁上的金属镀层的厚度。

公开(公告)号：US08987608B2

公开(公告)日：2015-03-24

申请号：US13615722

申请日：2012-09-14

Applicant: Shang-Feng Huang ,  Cheng-Po Yu ,  Jen-Chi Cheng

Inventor： Shang-Feng Huang ,  Cheng-Po Yu ,  Jen-Chi Cheng

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/46

CPC classification number: H05K1/0221 ,  H05K3/4644 ,  Y10T29/49155

Abstract: A circuit structure includes an inner circuit layer, a first and a second dielectric layers, a first and a second conductive material layers, and a second and a third conductive layers. The first dielectric layer covers a first conductive layer of the inner circuit layer and has a first surface and first circuit grooves. The first conductive material layer is disposed inside the first circuit grooves. The second conductive layer is disposed on the first surface and includes a signal trace and at least two reference traces. The second dielectric layer covers the first surface and the second conductive layer and has a second surface and second circuit grooves. Widths of the first and the second circuit grooves are smaller than that of the reference traces. The second conductive material layer is disposed inside the second circuit grooves. The third conductive layer is disposed on the second surface.

Abstract translation: 电路结构包括内部电路层，第一和第二电介质层，第一和第二导电材料层以及第二和第三导电层。 第一电介质层覆盖内电路层的第一导电层，并具有第一表面和第一电路槽。 第一导电材料层设置在第一电路槽的内部。 第二导电层设置在第一表面上并且包括信号迹线和至少两个参考迹线。 第二电介质层覆盖第一表面和第二导电层，并具有第二表面和第二电路槽。 第一和第二电路槽的宽度小于参考轨迹的宽度。 第二导电材料层设置在第二电路槽的内部。 第三导电层设置在第二表面上。

公开(公告)号：US08373071B2

公开(公告)日：2013-02-12

申请号：US12696629

申请日：2010-01-29

Applicant: Cheng-Po Yu ,  Chai-Liang Hsu

Inventor： Cheng-Po Yu ,  Chai-Liang Hsu

IPC: H05K1/00

CPC classification number: H05K3/107 ,  H05K3/181 ,  H05K3/422 ,  H05K2201/0376

Abstract: A method for manufacturing an embedded wiring board is provided. An activating insulation layer is formed, in which the activating insulation layer includes a plurality of catalyst particles, and covers a first wiring layer. An intaglio pattern and at least one blind via partially exposing the first wiring layer are formed on the activating insulation layer, in which some of the catalyst particles are activated and exposed in the intaglio pattern and the blind via. The activating insulation layer is dipped in a first chemical plating solution, and a solid conductive pillar is formed in the blind via through electroless plating. The activating insulation layer is dipped in a second chemical plating solution after the solid conductive pillar is formed, and a second wiring layer is formed in the intaglio pattern through the electroless plating. Components of the first chemical plating solution and the second chemical plating solution are different.

Abstract translation: 提供了一种用于制造嵌入式布线板的方法。 形成激活绝缘层，其中活化绝缘层包括多个催化剂颗粒，并覆盖第一布线层。 在活化绝缘层上形成凹版图案和部分露出第一布线层的至少一个盲孔，其中一些催化剂颗粒被活化并以凹版图案和盲孔曝光。 将激活绝缘层浸入第一化学镀溶液中，并通过化学镀在盲孔中形成固体导电柱。 在形成固体导电柱之后，将激活绝缘层浸入第二化学镀溶液中，并且通过无电解电镀在凹版图案中形成第二布线层。 第一化学镀液和第二化学镀液的成分不同。

公开(公告)号：US08171626B1

公开(公告)日：2012-05-08

申请号：US13155375

申请日：2011-06-07

Applicant: Cheng-Po Yu ,  Chi-Min Chang

Inventor： Cheng-Po Yu ,  Chi-Min Chang

IPC: H05K3/02 ,  H05K3/10 ,  H05K3/00 ,  H01R9/00 ,  H01R43/00

CPC classification number: H05K3/465 ,  H05K3/107 ,  H05K2201/0347 ,  Y10T29/49117 ,  Y10T29/49147 ,  Y10T29/49155

Abstract: A method for forming an embedded circuit is disclosed. First, a substrate including a dielectric layer is provided. Second, the dielectric layer is entirely covered by a dummy layer. Then, the dummy layer is patterned and a trench is formed in the dielectric layer at the same time. Later, a seed layer is formed to entirely cover the dummy layer and the trench. Next, the dummy layer is removed and the seed layer covering the dummy layer is removed, too. Afterwards, a metal layer is filled in the trench to form an embedded circuit embedded in the dielectric layer.

Abstract translation: 公开了一种用于形成嵌入式电路的方法。 首先，提供包括电介质层的基板。 第二，介电层完全被虚拟层覆盖。 然后，对虚拟层进行图案化，同时在电介质层中形成沟槽。 之后，形成种子层以完全覆盖虚设层和沟槽。 接下来，去除虚拟层，并且去除覆盖虚拟层的种子层。 之后，在沟槽中填充金属层，形成嵌入电介质层的嵌入电路。

公开(公告)号：US20070281388A1

公开(公告)日：2007-12-06

申请号：US11456213

申请日：2006-07-10

Applicant: Cheng-Po Yu ,  Cheng-Hung Yu ,  Chi-Min Chang

Inventor： Cheng-Po Yu ,  Cheng-Hung Yu ,  Chi-Min Chang

IPC: H01L21/00 ,  H01L21/4763

CPC classification number: H05K3/243 ,  H01L21/6715 ,  H05K3/0076 ,  H05K3/0079 ,  H05K3/28 ,  H05K2201/0391 ,  H05K2203/013 ,  H05K2203/058

Abstract: A selective metal surface treatment process of a circuit board, which has a solder mask and a multiple of selective metal treatment surface areas, wherein the solder mask covers the surface of the circuit board but exposes the selective metal surface treatment areas, is provided. The selective metal surface treatment process includes using a printhead to selectively print a resist on a selective metal surface treatment area, performing a surface treatment of the other selective metal surface treatment areas, and removing the resist. A selective metal surface treatment apparatus used for performing the selective metal surface treatment process of the circuit board is also provided. Through the present invention, unnecessary waste of the materials in the process is reduced and the processing time is shortened.

Abstract translation: 提供具有焊接掩模和多个选择性金属处理表面积的电路板的选择性金属表面处理工艺，其中焊接掩模覆盖电路板的表面，但暴露选择性金属表面处理区域。 选择性金属表面处理方法包括使用打印头选择性地在选择性金属表面处理区域上印刷抗蚀剂，对其它选择性金属表面处理区域进行表面处理，并除去抗蚀剂。 还提供了用于执行电路板的选择性金属表面处理工艺的选择性金属表面处理装置。 通过本发明，可以减少处理过程中不必要的材料浪费，缩短处理时间。

公开(公告)号：US08963019B2

公开(公告)日：2015-02-24

申请号：US13570251

申请日：2012-08-09

Applicant: Cheng-Po Yu ,  Shang-Feng Huang ,  Chang-Ming Lee ,  Young-Sheng Bai

Inventor： Cheng-Po Yu ,  Shang-Feng Huang ,  Chang-Ming Lee ,  Young-Sheng Bai

IPC: H05K1/11 ,  H05K3/00

CPC classification number: H05K3/381 ,  H05K3/105 ,  H05K3/108 ,  H05K2201/0215 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/095 ,  H05K2203/1461

Abstract: A circuit board and a manufacturing method thereof are provided. According to the method, a dielectric layer is formed on a dielectric substrate, and the dielectric layer contains active particles. A surface treatment is performed on a surface of the dielectric first conductive layer is formed on the activated surface of the dielectric layer. A conductive via is formed in the dielectric substrate and the dielectric layer. A patterned mask layer is formed on the first conductive layer, in which the patterned mask layer exposes the conductive via and a part of the first conductive layer. A second conductive layer is formed on the first conductive layer and conductive via exposed by the patterned mask layer. The patterned mask layer and the first conductive layer below the patterned mask layer are removed.

Abstract translation: 提供一种电路板及其制造方法。 根据该方法，在电介质基板上形成介电层，电介质层含有活性粒子。 在电介质层的活化表面上形成电介质第一导电层的表面进行表面处理。 在电介质基板和电介质层中形成导电通孔。 图案化的掩模层形成在第一导电层上，其中图案化掩模层暴露导电通孔和第一导电层的一部分。 在第一导电层上形成第二导电层，并且由图案化掩模层暴露出导电通路。 图案化掩模层和图案化掩模层下面的第一导电层被去除。

公开(公告)号：US08450621B2

公开(公告)日：2013-05-28

申请号：US12328446

申请日：2008-12-04

Applicant: Tsung-Yuan Chen ,  Chun-Chien Chen ,  Cheng-Po Yu

Inventor： Tsung-Yuan Chen ,  Chun-Chien Chen ,  Cheng-Po Yu

IPC: H05K1/00 ,  H05K1/03 ,  H05K1/09 ,  H05K1/14 ,  H05K7/00 ,  H05K1/18

CPC classification number: H05K3/428 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/20 ,  H05K3/205 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/0969 ,  H05K2203/0369 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0554 ,  H05K2203/108 ,  H05K2203/1476 ,  Y10T29/49124 ,  Y10T29/49126

Abstract: A process for fabricating a wiring board is provided. In the process, a wiring carrying substrate including a carry substrate and a wiring layer is formed. Next, at least one blind via is formed in the wiring carrying substrate. Next, the wiring carrying substrate is laminated to another wiring carrying substrate via an insulation layer. The insulation layer is disposed between the wiring layers of the wiring carrying substrates and full fills the blind via. Next, parts of the carry substrates are removed to expose the insulation layer in the blind via. Next, a conductive pillar connected between the wiring layers is formed. Next, the rest carry substrates are removed.

Abstract translation: 提供一种制造布线板的工艺。 在该过程中，形成包括携带衬底和布线层的布线承载衬底。 接下来，在布线承载基板中形成至少一个盲孔。 接下来，通过绝缘层将布线承载基板层叠到另一布线承载基板。 绝缘层设置在布线基板的布线层之间，并且完全填充盲孔。 接下来，去除部分搬运基板以露出盲孔中的绝缘层。 接下来，形成连接在布线层之间的导电柱。 接下来，其余的携带衬底被去除。

公开(公告)号：US08294041B2

公开(公告)日：2012-10-23

申请号：US12170082

申请日：2008-07-09

Applicant: Cheng-Po Yu ,  Cheng-Hung Yu

Inventor： Cheng-Po Yu ,  Cheng-Hung Yu

IPC: H05K1/11

CPC classification number: H05K1/0231 ,  H05K1/0219 ,  H05K1/162 ,  H05K3/107 ,  H05K2201/09036 ,  H05K2201/09809 ,  Y10T29/49117

Abstract: A circuit board including a first dielectric layer having a first surface and a second surface, a first circuit layer, a second dielectric layer, and a second circuit layer is provided. At least one trench is formed on the first surface, and the first circuit layer is formed on an inside wall of the trench. In addition, the second dielectric layer is disposed in the trench, and covers the first circuit layer. The second circuit layer is disposed in the trench, and the second dielectric layer is located between the first circuit layer and the second circuit layer. A manufacturing method of the circuit board is further provided.

Abstract translation: 提供一种电路板，包括具有第一表面和第二表面的第一介电层，第一电路层，第二电介质层和第二电路层。 在第一表面上形成至少一个沟槽，并且第一电路层形成在沟槽的内壁上。 此外，第二电介质层设置在沟槽中并覆盖第一电路层。 第二电路层设置在沟槽中，第二电介质层位于第一电路层和第二电路层之间。 还提供了电路板的制造方法。

公开(公告)号：US20120231179A1

公开(公告)日：2012-09-13

申请号：US13474735

申请日：2012-05-18

Applicant: Cheng-Po Yu

Inventor： Cheng-Po Yu

IPC: H05K3/00 ,  C25D5/02 ,  B05D3/06

CPC classification number: H05K3/0035 ,  H05K3/107 ,  H05K3/465 ,  H05K2201/0236 ,  H05K2201/0959 ,  H05K2201/09845 ,  H05K2203/1476 ,  Y10T29/49155

Abstract: An embedded wiring board includes an upper wiring layer, a lower wiring layer, an insulation layer, a first conductive pillar and a second conductive pillar. The upper wiring layer contains an upper pad, the lower wiring layer contains a lower pad, and the insulation layer contains an upper surface and a lower surface opposite to the upper surface. The upper pad is embedded in the upper surface and the lower pad is embedded in the lower surface. The first conductive pillar is located in the insulation layer and includes an end surface which is exposed by the upper surface. A height of the first conductive pillar relative to the upper surface is larger than a depth of the upper pad relative to the upper surface. In addition, the second conductive pillar is located in the insulation layer and is connected between the first conductive pillar and the lower pad.

Abstract translation: 嵌入布线板包括上布线层，下布线层，绝缘层，第一导电柱和第二导电柱。 上布线层包含上焊盘，下布线层包含下焊盘，绝缘层包含与上表面相对的上表面和下表面。 上垫片嵌入在上表面中，下垫片嵌入下表面。 第一导电柱位于绝缘层中，并且包括由上表面暴露的端面。 第一导电柱相对于上表面的高度大于上垫相对于上表面的深度。 此外，第二导电柱位于绝缘层中并连接在第一导电柱和下垫之间。

公开(公告)号：US20120067630A1

公开(公告)日：2012-03-22

申请号：US13305310

申请日：2011-11-28

Applicant: Cheng-Po Yu

Inventor： Cheng-Po Yu

IPC: H05K1/09 ,  H05K1/00

CPC classification number: H05K3/107 ,  H05K1/0265 ,  H05K3/0032 ,  H05K3/06 ,  H05K3/061 ,  H05K2201/0376 ,  H05K2201/09727 ,  H05K2203/0369 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A circuit structure of a circuit board includes a dielectric layer, a number of first circuits, and a number of second circuits. The dielectric layer has a surface and an intaglio pattern. The first circuits are disposed on the surface of the dielectric layer. The second circuits are disposed in the intaglio pattern of the dielectric layer. Line widths of the second circuits are smaller than line widths of the first circuits, and a distance between every two of the adjacent second circuits is shorter than a distance between every two of the adjacent first circuits.

Abstract translation: 电路板的电路结构包括电介质层，多个第一电路和多个第二电路。 电介质层具有表面和凹版图案。 第一电路设置在电介质层的表面上。 第二电路设置在电介质层的凹版图案中。 第二电路的线宽小于第一电路的线宽，并且相邻的第二电路中的每两个之间的距离比相邻的第一电路中的每两个之间的距离短。