公开(公告)号：US20160329400A1

公开(公告)日：2016-11-10

申请号：US15215609

申请日：2016-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsai-Yu Wen ,  Chin-Sheng Yang ,  Chun-Jen Chen ,  Tsuo-Wen Lu ,  Yu-Ren Wang

IPC: H01L29/06 ,  H01L29/161 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02603 ,  H01L21/02612 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/31658 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire.

Abstract translation: 形成纳米线的方法包括提供基底。 蚀刻衬底以形成至少一个鳍。 随后，在鳍的上部形成第一外延层。 之后，在翅片的中间部分形成底切。 形成第二外延层以填充底切。 最后，将鳍状物，第一外延层和第二外延层氧化以将第一外延层和第二外延层冷凝成含锗纳米线。

公开(公告)号：US09117878B2

公开(公告)日：2015-08-25

申请号：US13710483

申请日：2012-12-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Keng-Jen Lin ,  Yu-Ren Wang ,  Chih-Chung Chen ,  Tsuo-Wen Lu ,  Tsai-Yu Wen

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/02 ,  H01L21/321

CPC classification number: H01L21/76232 ,  H01L21/02164 ,  H01L21/02219 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/32105

Abstract: A method for manufacturing a semiconductor structure includes the following steps. First, a semiconductor substrate is provided and a patterned pad layer is formed on the semiconductor substrate so as to expose a portion of the semiconductor substrate. Then, the semiconductor substrate exposed from the patterned pad layer is etched away to form a trench inside the semiconductor substrate. A selectively-grown material layer is selectively formed on the surface of the trench, followed by filling a dielectric precursor material into the trench. Finally, a transformation process is carried out to concurrently transform the dielectric precursor material into a dielectric material and transform the selectively-grown material layer into an oxygen-containing amorphous material layer.

Abstract translation: 一种制造半导体结构的方法包括以下步骤。 首先，提供半导体衬底，并且在半导体衬底上形成图案化衬垫层以露出半导体衬底的一部分。 然后，从图案化衬垫层露出的半导体衬底被蚀刻掉以在半导体衬底内部形成沟槽。 在沟槽的表面上选择性地形成选择性生长的材料层，然后将电介质前体材料填充到沟槽中。 最后，进行转换处理以将电介质前体材料同时转变为电介质材料，并将选择性生长的材料层转变成含氧非晶材料层。

公开(公告)号：US20150021776A1

公开(公告)日：2015-01-22

申请号：US14507317

申请日：2014-10-06

Applicant: United Microelectronics Corp.

Inventor： Chien-Liang Lin ,  Yu-Ren Wang ,  Ying-Wei Yen ,  Wen-Yi Teng ,  Chan-Lon Yang

IPC: H01L29/49

CPC classification number: H01L29/4916 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/28035 ,  H01L29/4925

Abstract: A polysilicon layer including an amorphous polysilicon layer and a crystallized polysilicon layer is provided. The crystallized polysilicon layer is disposed on the amorphous polysilicon layer. Besides, the amorphous polysilicon layer has a first grain size, the crystallized polysilicon layer has a second grain size, and the first grain size is smaller than the second grain size. The amorphous polysilicon layer with a smaller grain size can serve as a base for the following deposition, so that the crystallized polysilicon layer formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved.

Abstract translation: 提供了包括非晶多晶硅层和结晶的多晶硅层的多晶硅层。 结晶的多晶硅层设置在非晶多晶硅层上。 此外，非晶多晶硅层具有第一晶粒尺寸，结晶的多晶硅层具有第二晶粒尺寸，并且第一晶粒尺寸小于第二晶粒尺寸。 具有较小晶粒尺寸的非晶多晶硅层可以用作随后沉积的基底，使得其上形成的结晶多晶硅层具有更平坦的形貌，因此表面粗糙度降低，晶片内的Rs均匀性提高。

公开(公告)号：US20140162431A1

公开(公告)日：2014-06-12

申请号：US13710483

申请日：2012-12-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Keng-Jen Lin ,  Yu-Ren Wang ,  Chih-Chung Chen ,  Tsuo-Wen Lu ,  Tsai-Yu Wen

IPC: H01L21/762

CPC classification number: H01L21/76232 ,  H01L21/02164 ,  H01L21/02219 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/32105

Abstract: A method for manufacturing a semiconductor structure includes the following steps. First, a semiconductor substrate is provided and a patterned pad layer is formed on the semiconductor substrate so as to expose a portion of the semiconductor substrate. Then, the semiconductor substrate exposed from the patterned pad layer is etched away to form a trench inside the semiconductor substrate. A selectively-grown material layer is selectively formed on the surface of the trench, followed by filling a dielectric precursor material into the trench. Finally, a transformation process is carried out to concurrently transform the dielectric precursor material into a dielectric material and transform the selectively-grown material layer into an oxygen-containing amorphous material layer.

Abstract translation: 一种制造半导体结构的方法包括以下步骤。 首先，提供半导体衬底，并且在半导体衬底上形成图案化衬垫层以露出半导体衬底的一部分。 然后，从图案化衬垫层露出的半导体衬底被蚀刻掉以在半导体衬底内部形成沟槽。 在沟槽的表面上选择性地形成选择性生长的材料层，然后将电介质前体材料填充到沟槽中。 最后，进行转换处理以将电介质前体材料同时转变为电介质材料，并将选择性生长的材料层转变成含氧非晶材料层。

公开(公告)号：US12237398B2

公开(公告)日：2025-02-25

申请号：US17338691

申请日：2021-06-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ming Kuo ,  Po-Jen Chuang ,  Yu-Ren Wang ,  Ying-Wei Yen ,  Fu-Jung Chuang ,  Ya-Yin Hsiao ,  Nan-Yuan Huang

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/28 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/324 ,  H01L29/08 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/423

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer adjacent to the gate structure, wherein the first spacer comprises silicon carbon nitride (SiCN); forming a second spacer adjacent to the first spacer, wherein the second spacer comprises silicon oxycarbonitride (SiOCN); and forming a source/drain region adjacent to two sides of the second spacer.

公开(公告)号：US12159930B2

公开(公告)日：2024-12-03

申请号：US17897237

申请日：2022-08-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ming Hsu ,  Yen-Hsing Chen ,  Tsung-Mu Yang ,  Yu-Ren Wang

IPC: H01L29/66 ,  H01L29/16 ,  H01L29/20 ,  H01L29/778

Abstract: A high electron mobility transistor (HEMT) includes a substrate, a P-type III-V composition layer, a gate electrode and a carbon containing layer. The P-type III-V composition layer is disposed on the substrate, and the gate electrode is disposed on the P-type III-V composition layer. The carbon containing layer is disposed under the P-type III-V composition layer to function like an out diffusion barrier for preventing from the dopant within the P-type III-V composition layer diffusing into the stacked layers underneath during the annealing process.

公开(公告)号：US20240234505A1

公开(公告)日：2024-07-11

申请号：US18105887

申请日：2023-02-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsu Ting ,  Kuang-Hsiu Chen ,  Shou-Hung Wu ,  Shao-Wei Wang ,  Yu-Ren Wang

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device includes a fin structure disposed on a substrate, and an epitaxial semiconductor layer disposed over an upper part of the fin structure and having an undercut. The epitaxial semiconductor layer has a right-left symmetric, concave polygonal cross-section.

公开(公告)号：US20230020271A1

公开(公告)日：2023-01-19

申请号：US17949241

申请日：2022-09-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Hsing Chen ,  Yu-Ming Hsu ,  Tsung-Mu Yang ,  Yu-Ren Wang

IPC: H01L29/778 ,  H01L21/768 ,  H01L29/66 ,  H01L21/67

Abstract: A high-electron mobility transistor includes a substrate; a channel layer on the substrate; a AlGaN layer on the channel layer; and a P—GaN gate on the AlGaN layer. The AlGaN layer comprises a first region and a second region. The first region has a composition that is different from that of the second region.

公开(公告)号：US11355626B2

公开(公告)日：2022-06-07

申请号：US16574094

申请日：2019-09-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ming Hsu ,  Yu-Chi Wang ,  Yen-Hsing Chen ,  Tsung-Mu Yang ,  Yu-Ren Wang

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/267 ,  H01L29/15 ,  H01L29/20 ,  H01L29/04

Abstract: An HEMT includes an aluminum gallium nitride layer. A gallium nitride layer is disposed below the aluminum gallium nitride layer. A zinc oxide layer is disposed under the gallium nitride layer. A source electrode and a drain electrode are disposed on the aluminum gallium nitride layer. A gate electrode is disposed on the aluminum gallium nitride layer and between the drain electrode and the source electrode.

公开(公告)号：US20210296466A1

公开(公告)日：2021-09-23

申请号：US17338691

申请日：2021-06-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ming Kuo ,  Po-Jen Chuang ,  Yu-Ren Wang ,  Ying-Wei Yen ,  Fu-Jung Chuang ,  Ya-Yin Hsiao ,  Nan-Yuan Huang

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L29/08 ,  H01L29/78

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer adjacent to the gate structure, wherein the first spacer comprises silicon carbon nitride (SiCN); forming a second spacer adjacent to the first spacer, wherein the second spacer comprises silicon oxycarbonitride (SiOCN); and forming a source/drain region adjacent to two sides of the second spacer.