公开(公告)号：US11004805B2

公开(公告)日：2021-05-11

申请号：US16542305

申请日：2019-08-16

Applicant: Winbond Electronics Corp.

Inventor： Yao-Ting Tsai ,  Chiang-Hung Chen ,  Che-Fu Chuang ,  Wen Hung

IPC: H01L23/00 ,  H01L21/74

Abstract: Provided is a method of fabricating a semiconductor device, including the following steps. A first seal ring and a second seal ring that are separated from each other are formed on a substrate. A protective layer covering the first seal ring and the second seal ring is formed on the substrate. The protective layer between the first seal ring and the second seal ring includes a concave surface. The protective layer at the concave surface and a portion of the protective layer on the first seal ring are removed to form a spacer on a sidewall of the first seal ring, and form an opening in the protective layer. The width of the opening is greater than the width of the first seal ring, and the opening exposes a top surface of the first seal ring and the spacer.

公开(公告)号：US20210050307A1

公开(公告)日：2021-02-18

申请号：US16542305

申请日：2019-08-16

Applicant: Winbond Electronics Corp.

Inventor： Yao-Ting Tsai ,  Chiang-Hung Chen ,  Che-Fu Chuang ,  Wen Hung

IPC: H01L23/00 ,  H01L21/74

Abstract: Provided is a method of fabricating a semiconductor device, including the following steps. A first seal ring and a second seal ring that are separated from each other are formed on a substrate. A protective layer covering the first seal ring and the second seal ring is formed on the substrate. The protective layer between the first seal ring and the second seal ring includes a concave surface. The protective layer at the concave surface and a portion of the protective layer on the first seal ring are removed to form a spacer on a sidewall of the first seal ring, and form an opening in the protective layer. The width of the opening is greater than the width of the first seal ring, and the opening exposes a top surface of the first seal ring and the spacer.

公开(公告)号：US10580487B2

公开(公告)日：2020-03-03

申请号：US16048364

申请日：2018-07-30

Applicant: Winbond Electronics Corp.

Inventor： Chiang-Hung Chen ,  Yao-Ting Tsai ,  Wen Hung ,  Yu-Kai Liao

IPC: G11C11/56 ,  H01L21/3215 ,  H01L23/532 ,  H01L29/51 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L27/11582 ,  G11C16/04 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/528 ,  H01L21/28 ,  H01L29/423 ,  H01L27/11521 ,  H01L29/66 ,  H01L29/788

Abstract: A three dimensional memory includes a substrate, a plurality of source lines, a plurality of isolation structures, a plurality of drain lines, a plurality of bit lines, a plurality of charge storage structures, and a plurality of conductive layers. The source lines are located on the substrate. The isolation structures are respectively located between the source lines, so as to electrically isolate the source lines from each other. The drain lines are located on the source lines. Extending directions of the source lines and the drain lines are different. The bit lines extend from the source lines to the drain lines. The charge storage structures respectively surround the bit lines. The conductive layers respectively cover surfaces of the charge storage structures arranged along each of the source lines.

公开(公告)号：US12190981B2

公开(公告)日：2025-01-07

申请号：US17866558

申请日：2022-07-18

Applicant: Winbond Electronics Corp.

Inventor： Yao-Ting Tsai ,  Che-Fu Chuang

IPC: G11C8/12 ,  G11C5/06 ,  G11C29/00 ,  G11C29/24 ,  G11C29/52 ,  H10B41/10 ,  H10B41/42 ,  G11C8/14

Abstract: A memory array is provided. The memory array includes multiple memory blocks, each including multiple data storage regions and multiple groups of word lines. Each group of word lines extend across one of the memory blocks. The groups of word lines are connected to multiple overlying signal lines through multiple groups of first word line contact regions in the memory blocks and multiple second word line contact regions between the memory blocks.

公开(公告)号：US12040412B2

公开(公告)日：2024-07-16

申请号：US17375000

申请日：2021-07-14

Applicant: Winbond Electronics Corp.

Inventor： Yu-Lung Wang ,  Yao-Ting Tsai ,  Jian-Ting Chen ,  Yuan-Huang Wei

IPC: H01L29/78 ,  H01L21/311 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/788 ,  H10B41/30

CPC classification number: H01L29/788 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/6653 ,  H10B41/30

Abstract: Provided is a semiconductor device including a substrate, multiple first gate structures, and a protective structure. The substrate includes a first region and a second region. The first gate structures are disposed on the substrate in the first region. The protective structure conformally covers a sidewall of one of the first gate structures adjacent to the second region. The protective structure includes a lower portion and an upper portion disposed on the lower portion. The lower portion and the upper portion have different dielectric materials. A method of forming a semiconductor device is also provided.

公开(公告)号：US11877447B2

公开(公告)日：2024-01-16

申请号：US18297659

申请日：2023-04-10

Applicant: Winbond Electronics Corp.

Inventor： Yao-Ting Tsai ,  Hsiu-Han Liao ,  Che-Fu Chuang

IPC: H01L21/00 ,  H10B41/42 ,  H01L29/66 ,  H01L29/788 ,  H10B41/30

CPC classification number: H10B41/42 ,  H01L29/66825 ,  H01L29/7883 ,  H10B41/30

Abstract: Disposed are a semiconductor structure, a manufacturing method thereof and a flash memory. The semiconductor structure includes a substrate, first isolation structures, a gate structure and an oxide layer. The first isolation structures define a first active area in a peripheral region of the substrate. The oxide layer is disposed on the substrate in the first active area and covered by the first isolation structures. The oxide layer and the first isolation structures define an opening exposing the substrate. The gate structure is disposed on the substrate in the first active area and includes a gate dielectric layer disposed in the opening and a gate disposed on the gate dielectric layer. The oxide layer is located around the gate dielectric layer. The width of the bottom surface of the gate is less than that of the top surface of the first active area.

公开(公告)号：US11839075B2

公开(公告)日：2023-12-05

申请号：US17685786

申请日：2022-03-03

Applicant: Winbond Electronics Corp.

Inventor： Chih-Jung Ni ,  Chuan-Chi Chou ,  Yao-Ting Tsai

IPC: H10B41/30 ,  G11C5/06 ,  H10B41/40

CPC classification number: H10B41/30 ,  G11C5/063 ,  H10B41/40

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a gate structure, and a first spacer. The gate structure includes a floating gate structure disposed on the substrate, an inter-gate dielectric layer disposed on the floating gate structure, and a control gate structure disposed on the inter-gate dielectric layer. The control gate structure includes an electrode layer disposed on the inter-gate dielectric layer, a contact layer disposed on the electrode layer, and a cap layer disposed on the contact layer. The first spacer is disposed on a sidewall of the control gate structure and covering the electrode, the contact layer and the cap layer. A bottom surface of the first spacer is positioned between a bottom surface and a top surface of the electrode layer.

公开(公告)号：US20230255026A1

公开(公告)日：2023-08-10

申请号：US18297659

申请日：2023-04-10

Applicant: Winbond Electronics Corp.

Inventor： Yao-Ting Tsai ,  Hsiu-Han Liao ,  Che-Fu Chuang

IPC: H10B41/42 ,  H01L29/66 ,  H01L29/788 ,  H10B41/30

CPC classification number: H10B41/42 ,  H01L29/66825 ,  H01L29/7883 ,  H10B41/30

Abstract: Disposed are a semiconductor structure, a manufacturing method thereof and a flash memory. The semiconductor structure includes a substrate, first isolation structures, a gate structure and an oxide layer. The first isolation structures define a first active area in a peripheral region of the substrate. The oxide layer is disposed on the substrate in the first active area and covered by the first isolation structures. The oxide layer and the first isolation structures define an opening exposing the substrate. The gate structure is disposed on the substrate in the first active area and includes a gate dielectric layer disposed in the opening and a gate disposed on the gate dielectric layer. The oxide layer is located around the gate dielectric layer. The width of the bottom surface of the gate is less than that of the top surface of the first active area.

公开(公告)号：US20230209820A1

公开(公告)日：2023-06-29

申请号：US17564259

申请日：2021-12-29

Applicant: Winbond Electronics Corp.

Inventor： Che-Fu Chuang ,  Yao-Ting Tsai ,  Hsiu-Han Liao

IPC: H01L27/11521 ,  H01L29/417 ,  H01L29/788 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L27/11521 ,  H01L29/41725 ,  H01L29/7883 ,  H01L29/401 ,  H01L29/66825

Abstract: Provided are a memory device and a method of manufacturing the same. The memory device includes: a stack structure; a first source/drain region and a second source/drain region located in a substrate beside the stack structure; a first self-aligned contact connected to the first source/drain region; a second self-aligned contact connected to the second source/drain region; a first liner structure located between the first self-aligned contact and a first sidewall of the stack structure; and a second liner structure located between the second self-aligned contact and a second sidewall of the stack structure. The first liner structure and the second liner structure are not connected and do not cover the stack structure.

公开(公告)号：US11678484B2

公开(公告)日：2023-06-13

申请号：US17376079

申请日：2021-07-14

Applicant: Winbond Electronics Corp.

Inventor： Yao-Ting Tsai ,  Hsiu-Han Liao ,  Che-Fu Chuang

IPC: H01L21/00 ,  H10B41/42 ,  H01L29/66 ,  H01L29/788 ,  H10B41/30

CPC classification number: H10B41/42 ,  H01L29/66825 ,  H01L29/7883 ,  H10B41/30

Abstract: Disposed are a semiconductor structure, a manufacturing method thereof and a flash memory. The semiconductor structure includes a substrate, first isolation structures, a gate structure and an oxide layer. The first isolation structures define a first active area in a peripheral region of the substrate. The oxide layer is disposed on the substrate in the first active area and covered by the first isolation structures. The oxide layer and the first isolation structures define an opening exposing the substrate. The gate structure is disposed on the substrate in the first active area and includes a gate dielectric layer disposed in the opening and a gate disposed on the gate dielectric layer. The oxide layer is located around the gate dielectric layer. The width of the bottom surface of the gate is less than that of the top surface of the first active area.