公开(公告)号：US20060070875A1

公开(公告)日：2006-04-06

申请号：US11229139

申请日：2005-09-15

申请人： Jaim Nulman ,  Sergio Edelstein ,  Mani Subramani ,  Zheng Xu ,  Howard Grunes ,  Avi Tepman ,  John Forster ,  Praburam Gopalraja

发明人： Jaim Nulman ,  Sergio Edelstein ,  Mani Subramani ,  Zheng Xu ,  Howard Grunes ,  Avi Tepman ,  John Forster ,  Praburam Gopalraja

IPC分类号： C23C14/00 ,  C25B11/00

CPC分类号： C23C14/34 ,  H01J37/321 ,  H01J37/34

摘要： A sputtering coil for a plasma chamber in a semiconductor fabrication system is provided. The sputtering coil couples energy into a plasma and also provides a source of sputtering material to be sputtered onto a workpiece from the coil to supplement material being sputtered from a target onto the workpiece. Alternatively a plurality of coils may be provided, one primarily for coupling energy into the plasma and the other primarily for providing a supplemental source of sputtering material to be sputtered on the workpiece.

公开(公告)号：US07006888B2

公开(公告)日：2006-02-28

申请号：US10046954

申请日：2002-01-14

申请人： Hougong Wang ,  Kenny King-Tai Ngan ,  Zheng Xu

发明人： Hougong Wang ,  Kenny King-Tai Ngan ,  Zheng Xu

IPC分类号： G06F19/00

CPC分类号： H01L21/67184 ,  H01L21/67201 ,  H01L21/67745 ,  Y10T29/41

摘要： Embodiments of the present invention provide a method, article of manufacture, and apparatus for processing semiconductor wafers. The method includes preheating a semiconductor wafer in two types of chambers. In one embodiment, a first preheating chamber is a load lock and a second preheating chamber is a transition chamber. Semiconductor wafer processing systems which can perform embodiments of the method are presented.

公开(公告)号：US20050085068A1

公开(公告)日：2005-04-21

申请号：US10981319

申请日：2004-11-03

申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen Chen ,  Barry Chin ,  Gene Kohara ,  Zheng Xu ,  Hong Zhang

发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen Chen ,  Barry Chin ,  Gene Kohara ,  Zheng Xu ,  Hong Zhang

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

摘要： We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, said method comprising the steps of a) applying a first portion of a sculptured layer with sufficiently low substrate bias that a surface onto which said sculptured layer is applied is not eroded away or contaminated in an amount which is harmful to said semiconductor device performance or longevity; and b) applying a subsequent portion of said sculptured layer with sufficiently high substrate bias to sculpture a shape from said the first portion, while depositing additional layer material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces and is especially helpful when the conductive layer is copper. In the application of a barrier layer, a first portion of barrier layer material is deposited on the substrate surface using standard sputtering techniques or using an ion deposition plasma, but in combination with sufficiently low substrate bias voltage (including at no applied substrate voltage) that the surfaces impacted by ions are not sputtered in an amount which is harmful to device performance or longevity. Subsequently, a second portion of barrier material is applied using ion deposition sputtering at increased substrate bias voltage which causes resputtering (sculpturing) of the first portion of barrier layer material, while enabling a more anisotropic deposition of newly depositing material. A conductive material, and particularly a copper seed layer applied to the feature may be accomplished using the same sculpturing technique as that described above with reference to the barrier layer.

摘要翻译： 我们公开了使用离子沉积溅射在半导体特征表面上施加雕刻层的材料的方法，其中施加有雕刻层的表面被保护以通过冲击沉积层的离子来抵抗侵蚀和污染，所述方法包括 步骤：a）以足够低的衬底偏压施加雕刻层的第一部分，使得施加所述雕刻层的表面不会以对所述半导体器件的性能或寿命有害的量被腐蚀掉或污染; 以及b）将所述雕刻层的后续部分施加足够高的衬底偏压，以从所述第一部分雕刻形状，同时沉积附加层材料。 该方法特别适用于在半导体特征表面上雕刻阻挡层，润湿层和导电层，并且当导电层是铜时尤其有用。 在施加阻挡层时，使用标准溅射技术或使用离子沉积等离子体将阻挡层材料的第一部分沉积在衬底表面上，但是与足够低的衬底偏置电压（包括没有施加的衬底电压）组合， 受离子影响的表面不会以对器件性能或寿命有害的量溅射。 随后，使用离子沉积溅射在增加的衬底偏置电压下施加阻挡材料的第二部分，这导致阻挡层材料的第一部分的再溅射（雕刻），同时能够进行更多的各向异性沉积新沉积的材料。 应用于特征的导电材料，特别是铜种子层可以使用与上述参考阻挡层所述相同的雕刻技术来实现。

公开(公告)号：US20050056536A1

公开(公告)日：2005-03-17

申请号：US10934231

申请日：2004-09-03

申请人： Praburam Gopalraja ,  Jianming Fu ,  Fusen Chen ,  Girish Dixit ,  Zheng Xu ,  Wei Wang ,  Ashok Sinha

发明人： Praburam Gopalraja ,  Jianming Fu ,  Fusen Chen ,  Girish Dixit ,  Zheng Xu ,  Wei Wang ,  Ashok Sinha

IPC分类号： C23C14/34 ,  C23C14/04 ,  C23C14/16 ,  C23C14/32 ,  C23C14/35 ,  H01J37/34 ,  H01L21/203 ,  H01L21/285 ,  H01L21/288 ,  H01L21/768

CPC分类号： H01L21/76844 ,  C23C14/046 ,  C23C14/165 ,  C23C14/185 ,  C23C14/225 ,  C23C14/35 ,  H01J37/3405 ,  H01J37/342 ,  H01J37/3423 ,  H01J37/3452 ,  H01J37/3455 ,  H01J37/3458 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76873 ,  H01L2221/1089

摘要： A multi-step sputtering process in plasma sputter reactor having target and magnetron operable in two modes, for example, in a substrate sputter etch and a substrate sputter deposition. The target has an annular vault facing the wafer to be sputter coated. Various types of magnetic means positioned around the vault create a magnetic field supporting a plasma extending over a large volume of the vault. An integrated copper via filling process with the inventive reactor or other reactor includes a first step of highly ionized sputter deposition of copper, which can optionally be used to remove the barrier layer at the bottom of the via, a second step of more neutral, lower-energy sputter deposition of copper to complete the seed layer, and a third step of electroplating copper into the hole to complete the metallization. The first two steps can be also used with barrier metals.

摘要翻译： 在等离子体溅射反应器中的多步骤溅射工艺，其具有可在两种模式中操作的靶和磁控管，例如在衬底溅射蚀刻和衬底溅射沉积中。 目标具有面向待溅射涂覆的晶片的环形保险库。 位于拱顶周围的各种类型的磁性装置产生一个支撑等离子体的磁场，该等离子体延伸在大容积的拱顶上。 与本发明的反应器或其它反应器的集成铜通孔填充方法包括铜的高度电离溅射沉积的第一步骤，其可任选地用于去除通孔底部的阻挡层，更中立的，更低的 铜的完全溅射沉积以完成种子层，以及将铜电镀到孔中以完成金属化的第三步骤。 前两个步骤也可以与阻隔金属一起使用。

公开(公告)号：US06372633B1

公开(公告)日：2002-04-16

申请号：US09111657

申请日：1998-07-08

申请人： Dan Maydan ,  Ashok K. Sinha ,  Zheng Xu ,  Liang-Yu Chen ,  Roderick Craig Mosely ,  Daniel Carl ,  Diana Xiaobing Ma ,  Yan Ye ,  Wen Chiang Tu

发明人： Dan Maydan ,  Ashok K. Sinha ,  Zheng Xu ,  Liang-Yu Chen ,  Roderick Craig Mosely ,  Daniel Carl ,  Diana Xiaobing Ma ,  Yan Ye ,  Wen Chiang Tu

IPC分类号： H01L214763

CPC分类号： H01L21/76838 ,  H01L21/32136 ,  H01L21/76885

摘要： The present invention provides a method and apparatus for forming reliable interconnects in which the overlap of the line over the plug or via is minimized or eliminated. In one aspect, a barrier plug comprised of a conductive material, such as tungsten, is deposited over the via to provide an etch stop during line etching and to prevent diffusion of the metal, such as copper, into the surrounding dielectric material if the line is misaligned over the via. Additionally, the barrier plug prevents an overall reduction in resistance of the interconnect and enables reactive ion etching to be employed to form the metal line. In another aspect, reactive ion etching techniques are employed to selectively etch the metal line and the barrier layer to provide a controlled etching process which exhibits selectivity for the metal line, then the barrier and then the via or plug.

摘要翻译： 本发明提供了一种用于形成可靠互连的方法和装置，其中使插塞或通孔上的线重叠最小化或消除。 在一个方面，由诸如钨的导电材料构成的阻挡塞沉积在通孔上，以在线蚀刻期间提供蚀刻停止并且防止金属（例如铜）扩散到周围的介电材料中，如果线 在通道上不对齐。 此外，阻挡塞防止互连的电阻的总体降低，并且能够使用反应离子蚀刻来形成金属线。 在另一方面，使用反应离子蚀刻技术来选择性地蚀刻金属线和阻挡层，以提供对金属线，然后是屏障，然后是通孔或插塞的选择性的受控蚀刻工艺。

公开(公告)号：US06277249B1

公开(公告)日：2001-08-21

申请号：US09518180

申请日：2000-03-02

申请人： Praburam Gopalraja ,  Jianming Fu ,  Fusen Chen ,  Girish Dixit ,  Zheng Xu ,  Sankaram Athreya ,  Wei D. Wang ,  Ashok K. Sinha

发明人： Praburam Gopalraja ,  Jianming Fu ,  Fusen Chen ,  Girish Dixit ,  Zheng Xu ,  Sankaram Athreya ,  Wei D. Wang ,  Ashok K. Sinha

IPC分类号： C23C1435

CPC分类号： H01L21/76844 ,  C23C14/35 ,  H01J37/3405 ,  H01J37/342 ,  H01J37/3423 ,  H01J37/3455 ,  H01J37/3458 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76873 ,  H01L2221/1089

摘要： A target and magnetron for a plasma sputter reactor. The target has an annular trough facing the wafer to be sputter coated. Various types of magnetic means positioned around the trough create a magnetic field supporting a plasma extending over a large volume of the trough. For example, the magnetic means may include magnets disposed on one side within a radially inner wall of the trough and on another side outside of a radially outer wall of the trough to create a magnetic field extending across the trough, to thereby support a high-density plasma extending from the top to the bottom of the trough. The large plasma volume increases the probability that the sputtered metal atoms will become ionized. The magnetic means may include a magnetic coil, may include additional magnets in back of the trough top wall to increase sputtering there, and may include confinement magnets near the bottom of the trough sidewalls. The magnets in back of the top wall may have an outer magnet surrounding an inner magnet of the opposite polarity. The high aspect ratio of the trough also reduces asymmetry in coating the sidewalls of a deep hole at the edge of the wafer. An integrated copper via filling process includes a first step of highly ionized sputter deposition of copper, a second step of more neutral, lower-energy sputter deposition of copper to complete the seed layer, and electroplating copper into the hole to complete the metallization.

摘要翻译： 用于等离子体溅射反应器的靶和磁控管。 目标具有面向待溅射涂覆的晶片的环形槽。 位于槽周围的各种磁性装置形成一个支撑等离子体的磁场，该等离子体延伸在大容积的槽上。 例如，磁性装置可以包括设置在槽的径向内壁中的一侧上并且在槽的径向外壁外侧的另一侧上的磁体，以产生延伸穿过槽的磁场， 密度等离子体从槽的顶部延伸到底部。 大的等离子体体积增加了溅射的金属原子将被电离的可能性。 磁性装置可以包括磁性线圈，可以在槽顶壁的后面包括另外的磁体，以在那里增加溅射，并且可以包括靠近槽侧壁底部的约束磁体。 顶壁后面的磁体可以具有围绕相反极性的内磁体的外磁体。 槽的高纵横比也降低了在晶片边缘涂覆深孔侧壁的不对称性。 集成的铜通孔填充工艺包括铜的高度电离溅射沉积的第一步骤，更中性的，更低能量的溅射沉积铜以完成种子层的第二步骤，以及将铜电镀到孔中以完成金属化。

公开(公告)号：US06232665B1

公开(公告)日：2001-05-15

申请号：US09328117

申请日：1999-06-08

申请人： Gongda Yao ,  Peijun Ding ,  Zheng Xu ,  Hoa Kieu

发明人： Gongda Yao ,  Peijun Ding ,  Zheng Xu ,  Hoa Kieu

IPC分类号： H01L2348

CPC分类号： H01L21/76843 ,  H01L21/76882 ,  H01L23/485 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process for fabricating metal plugs, such as aluminum plugs, in a semiconductor workpiece. The invention is suitable for filling narrow, high aspect ratio holes, and the invention minimizes the formation of TiAl3 or other products of interdiffusion between the plug and the wetting layer. First, an optional barrier layer is created by covering the bottom of a hole with a film containing titanium nitride doped with silicon. Second, a wetting layer is created by covering the side walls of a hole with a film containing titanium doped with silicon, in a Ti:Si molar ratio greater than 1:2. Preferably, the wetting layer is created by sputter deposition using a titanium sputtering target containing 0.1% to 20% wt silicon, most preferably 5% to 10% wt silicon. Third, the hole is filled by depositing a material consisting primarily of aluminum. The hole preferably is filled by sputter deposition using an aluminum sputtering target, optionally containing dopants such as copper. To facilitate filling the hole without voids, the aluminum sputter deposition preferably is performed “warm”, i.e., with the workpiece at a temperature below the melting point of aluminum but high enough to promote reflow of the deposited material. The silicon atoms in the wetting layer inhibit the titanium from reacting with the aluminum, and the wetting layer facilitates filling the hole with the aluminum material without leaving unfilled voids.

摘要翻译： 一种用于在半导体工件中制造诸如铝塞的金属插头的工艺。 本发明适用于填充狭窄的高纵横比孔，并且本发明使塞子和润湿层之间的TiAl 3或其他相互扩散产物的形成最小化。 首先，通过用含有掺杂硅的氮化钛的膜覆盖孔的底部来产生可选的阻挡层。 第二，通过用含有掺杂硅的钛的膜覆盖孔的侧壁，Ti：Si摩尔比大于1:2产生润湿层。 优选地，通过使用含有0.1重量％至20重量％硅，最优选5重量％至10重量％硅的钛溅射靶的溅射沉积来产生润湿层。 第三，通过沉积主要由铝构成的材料填充孔。 优选地，通过使用铝溅射靶的溅射沉积来填充孔，任选地含有诸如铜的掺杂剂。 为了方便填充孔而没有空隙，铝溅射沉积优选地进行“暖”，即工件在低于铝的熔点的温度下，但足够高以促进沉积材料的回流。 润湿层中的硅原子阻止钛与铝反应，并且润湿层有助于用铝材料填充孔而不留下未填充的空隙。

公开(公告)号：USD440582S1

公开(公告)日：2001-04-17

申请号：US29090631

申请日：1998-07-13

申请人： Praburam Gopalraja ,  Zheng Xu ,  Michael Rosenstein ,  John C. Forster ,  Peijun Ding

设计人： Praburam Gopalraja ,  Zheng Xu ,  Michael Rosenstein ,  John C. Forster ,  Peijun Ding

公开(公告)号：US06217721B1

公开(公告)日：2001-04-17

申请号：US08628835

申请日：1996-04-05

申请人： Zheng Xu ,  John Forster ,  Tse-Yong Yao ,  Jaim Nulman ,  Fusen Chen

发明人： Zheng Xu ,  John Forster ,  Tse-Yong Yao ,  Jaim Nulman ,  Fusen Chen

IPC分类号： C23C1434

CPC分类号： H01L21/2855 ,  C23C14/0036 ,  C23C14/046 ,  C23C14/0641 ,  C23C14/32 ,  C23C14/358 ,  H01J37/34 ,  H01J2237/32 ,  H01L21/28518 ,  H01L21/76846 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An aluminum sputtering process, particularly useful for filling vias and contacts of high aspect ratios formed through a dielectric layer and also usefull for forming interconnects that are highly resistant to electromigration. A liner or barrier layer is first deposited by a high-density plasma (HDP) physical vapor deposition (PVD, also called sputtering) process, such as is done with an inductively coupled plasma. If a contact is connected at its bottom to a silicon element, the first sublayer of the liner layer is a Ti layer, which is silicided to the silicon substrate. The second sublayer comprises TiN, which not only acts as a barrier against the migration of undesirable components into the underlying silicon but also when deposited with an HDP process and biased wafer forms a dense, smooth crystal structure. The third sublayer comprises Ti and preferably is graded from TiN to Ti. Over the liner layer, an aluminum layer is deposited in a standard, non-HDP process. The liner layer allows the hottest part of the aluminum deposition to be performed at a relatively low temperature between 320 and 500° C., preferably between 350 and 420° C., while still filling narrow plug holes, and the TiN does not need to be annealed to form an effective barrier against diffusion into the silicon. A horizontal interconnect formed by the inventive process is resistant to electromigration.

摘要翻译： 铝溅射工艺，特别适用于填充通过电介质层形成的高纵横比的通孔和触点，并且也可用于形成高度抵抗电迁移的互连。 衬垫或阻挡层首先通过高密度等离子体（HDP）物理气相沉积（PVD，也称为溅射）工艺沉积，例如用电感耦合等离子体进行。 如果接触件的底部连接到硅元件，衬垫层的第一子层是Ti层，硅层被硅化到硅衬底。 第二子层包括TiN，其不仅用作防止不期望的组分迁移到下面的硅中的阻挡层，而且当用HDP工艺沉积并且偏置的晶片形成致密的，平滑的晶体结构时。 第三子层包含Ti，优选从TiN到Ti分级。 在衬里层上，铝层以标准的非HDP工艺沉积。 衬垫层允许铝沉积的最热部分在320和500℃之间的较低温度下进行，优选在350和420℃之间，同时仍然填充窄的塞孔，并且TiN不需要 进行退火以形成抵抗硅中扩散的有效屏障。 由本发明方法形成的水平互连对于电迁移是耐受的。

公开(公告)号：US5976334A

公开(公告)日：1999-11-02

申请号：US978433

申请日：1997-11-25

申请人： Jianming Fu ,  Zheng Xu

发明人： Jianming Fu ,  Zheng Xu

IPC分类号： C23C14/32 ,  C23C14/34 ,  C23C14/54 ,  H01J37/34 ,  C23C14/00

CPC分类号： H01J37/3444 ,  C23C14/32 ,  C23C14/3457 ,  C23C14/54 ,  H01J37/3405

摘要： A plasma physical vapor deposition (PVD) reactor configured for self sustained sputtering in which no sputtering working gas is required but the sputtered ions are sufficient to sustain the sputtering from the target. According to the invention, the power applied to the sputtering target is monitored to determine if sustained self-sputtering is being maintained. If the electrical parameters or other parameters in the chamber indicate that the self-sustained plasma has collapsed, a reinitialization procedure is begun including: admitting a working gas such as argon into the chamber; again exciting the plasma; and then effectively eliminating the working gas.

摘要翻译： 等离子体物理气相沉积（PVD）反应器，其被配置用于不需要溅射工作气体的自持溅射，但溅射离子足以维持靶的溅射。 根据本发明，监测施加到溅射靶的功率，以确定是否保持持续的自溅射。 如果腔室中的电气参数或其他参数指示自持血浆已经塌缩，则开始重新初始化过程，包括：将诸如氩气的工作气体引入腔室; 再次激发等离子体; 然后有效地消除工作气体。