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21.发明授权Semiconductor package and method of forming similar structure for top and bottom bonding pads 有权半导体封装和形成顶部和底部焊盘的类似结构的方法公开(公告)号：US08039302B2
公开(公告)日：2011-10-18
申请号：US11952502
申请日：2007-12-07
IPC分类号： H01L21/00
CPC分类号： H01L23/5389 , H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/4951 , H01L23/49575 , H01L24/16 , H01L24/18 , H01L24/19 , H01L24/81 , H01L24/82 , H01L24/96 , H01L25/0657 , H01L25/105 , H01L2224/04105 , H01L2224/05001 , H01L2224/05008 , H01L2224/05024 , H01L2224/05026 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05569 , H01L2224/05572 , H01L2224/05639 , H01L2224/05644 , H01L2224/05655 , H01L2224/05666 , H01L2224/12105 , H01L2224/16225 , H01L2224/18 , H01L2224/2919 , H01L2224/32225 , H01L2224/73204 , H01L2224/81801 , H01L2225/06524 , H01L2225/1035 , H01L2225/1058 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/19107 , H01L2924/30105 , H01L2924/0665 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor package has a first semiconductor die mounted on a substrate. A conductive via is formed through the substrate. A first RDL is formed on a first surface of the substrate in electrical contact with the conductive via and the first semiconductor die. A second RDL is formed on a second surface of the substrate opposite the first surface of the substrate die in electrical contact with the conductive via. A second semiconductor die can be mounted on the substrate and electrically connected to the second RDL. Bonding pads are formed over the first and second surfaces of the substrate in electrical contact with the first and second RDLs, respectively. The bonding pads on opposite surfaces of the substrate are aligned. Solder bumps or bond wires can be formed on the bonding pads. The semiconductor packages can be stacked and electrically connected through the aligned bonding pads.
摘要翻译： 半导体封装具有安装在基板上的第一半导体管芯。 通过衬底形成导电通孔。 第一RDL形成在与导电通孔和第一半导体管芯电接触的基板的第一表面上。 第二RDL形成在与导电通孔电接触的与衬底管芯的第一表面相对的衬底的第二表面上。 第二半导体管芯可以安装在基板上并电连接到第二RDL。 接合焊盘分别形成在基板的第一和第二表面上，与第一和第二RDL电接触。 对准衬底的相对表面上的接合焊盘。 焊接凸块或接合线可以形成在焊盘上。 半导体封装可以通过对准的焊盘层叠并电连接。
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公开(公告)号：US20090243064A1
公开(公告)日：2009-10-01
申请号：US12060115
申请日：2008-03-31
CPC分类号： H01L23/3121 , H01L23/3128 , H01L23/4334 , H01L23/4952 , H01L23/49548 , H01L23/49575 , H01L24/16 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/91 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L2224/0401 , H01L2224/06135 , H01L2224/06136 , H01L2224/16145 , H01L2224/16225 , H01L2224/29111 , H01L2224/2919 , H01L2224/32014 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48095 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/4824 , H01L2224/48247 , H01L2224/49109 , H01L2224/4911 , H01L2224/49111 , H01L2224/73207 , H01L2224/73215 , H01L2224/73265 , H01L2224/83 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2225/1088 , H01L2924/01013 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/1515 , H01L2924/15311 , H01L2924/15724 , H01L2924/15747 , H01L2924/181 , H01L2924/1815 , H01L2924/19103 , H01L2924/19107 , H01L2924/30105 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2224/4826
摘要： A method of manufacturing a semiconductor package involves providing a substrate having a window. The substrate may include a leadframe having half-etched leads. First and second semiconductor devices are mounted to a top surface of the substrate on either side of the window using an adhesive. A third semiconductor device is mounted to the first and second semiconductor devices using an adhesive. The third semiconductor device is disposed over the window of the substrate. A wirebond or other electrical interconnect is formed between the third semiconductor device and a contact pad formed over a bottom surface of the substrate opposite the top surface of the substrate. The wirebond or other electrical interconnect passes through the window of the substrate. An encapsulant is deposited over the first, second, and third semiconductor devices.
摘要翻译： 制造半导体封装的方法包括提供具有窗口的基板。 衬底可以包括具有半蚀刻引线的引线框架。 使用粘合剂将第一和第二半导体器件安装到窗口两侧的基板的顶表面。 使用粘合剂将第三半导体器件安装到第一和第二半导体器件。 第三半导体器件设置在衬底的窗口之上。 在第三半导体器件和形成在衬底的与衬底的顶表面相对的底表面上的接触焊盘之间形成引线接合或其它电互连。 引线键或其他电互连通过基板的窗口。 密封剂沉积在第一，第二和第三半导体器件上。
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23.发明申请Optical Semiconductor Device having Pre-Molded Leadframe with Window and Method Therefor 有权具有带窗口的预成型引线框的光半导体器件及其方法公开(公告)号：US20120168806A1
公开(公告)日：2012-07-05
申请号：US13419242
申请日：2012-03-13
IPC分类号： H01L31/18 , H01L31/0232
CPC分类号： H01L31/0203 , H01L21/563 , H01L23/3121 , H01L24/32 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/16245 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2924/00014 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15151 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/05599
摘要： A semiconductor device is made by providing a semiconductor die having an optically active area, providing a leadframe or pre-molded laminated substrate having a plurality of contact pads and a light transmitting material disposed between the contact pads, attaching the semiconductor die to the leadframe so that the optically active area is aligned with the light transmitting material to provide a light transmission path to the optically active area, and disposing an underfill material between the semiconductor die and leadframe. The light transmitting material includes an elevated area to prevent the underfill material from blocking the light transmission path. The elevated area includes a dam surrounding the light transmission path, an adhesive ring, or the light transmission path itself can be the elevated area. An adhesive ring can be disposed on the dam. A filler material can be disposed between the light transmitting material and contact pads.
摘要翻译： 通过提供具有光学活性区域的半导体管芯制造半导体器件，提供具有多个接触焊盘的引线框架或预成型层叠基板和设置在接触焊盘之间的透光材料，将半导体管芯附接到引线框架 光学活性区域与透光材料对准以提供到光学有效区域的光传输路径，并且在半导体管芯和引线框架之间设置底部填充材料。 透光材料包括用于防止底部填充材料阻挡光传输路径的升高区域。 升高区域包括围绕光传输路径的堤坝，粘合环，或者光传输路径本身可以是高架区域。 可以在大坝上设置粘合环。 填充材料可以设置在透光材料和接触垫之间。
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公开(公告)号：US07517733B2
公开(公告)日：2009-04-14
申请号：US11689645
申请日：2007-03-22
CPC分类号： H01L23/49551 , H01L23/3121 , H01L23/49811 , H01L24/48 , H01L25/03 , H01L25/105 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2225/1029 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package includes a leadframe. A first lead finger has a lower portion, a connecting portion extending vertically upward from the lower portion, and a substantially flat, top portion. The top portion forms a top terminal lead structure. A second lead finger is electrically connected to the first lead finger. A portion of the second lead finger forms a bottom terminal lead structure. A portion of the second lead finger corresponds to a bottom surface of the semiconductor package. A surface of the substantially flat, top portion corresponds to a top surface of the semiconductor package.
摘要翻译： 半导体封装包括引线框架。 第一引线指具有下部，从下部垂直向上延伸的连接部分和基本平坦的顶部。 顶部形成顶部端子引线结构。 第二引线指电连接到第一引线指。 第二引线指的一部分形成底部端子引线结构。 第二引线指的一部分对应于半导体封装的底表面。 基本平坦的顶部的表面对应于半导体封装的顶表面。
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25.发明申请Semiconductor Package and Method of Forming Similar Structure for Top and Bottom Bonding Pads 有权半导体封装和形成顶部和底部粘结垫的相似结构的方法公开(公告)号：US20120001326A1
公开(公告)日：2012-01-05
申请号：US13235413
申请日：2011-09-18
IPC分类号： H01L23/485 , H01L23/48
CPC分类号： H01L23/5389 , H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/4951 , H01L23/49575 , H01L24/16 , H01L24/18 , H01L24/19 , H01L24/81 , H01L24/82 , H01L24/96 , H01L25/0657 , H01L25/105 , H01L2224/04105 , H01L2224/05001 , H01L2224/05008 , H01L2224/05024 , H01L2224/05026 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05569 , H01L2224/05572 , H01L2224/05639 , H01L2224/05644 , H01L2224/05655 , H01L2224/05666 , H01L2224/12105 , H01L2224/16225 , H01L2224/18 , H01L2224/2919 , H01L2224/32225 , H01L2224/73204 , H01L2224/81801 , H01L2225/06524 , H01L2225/1035 , H01L2225/1058 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/19107 , H01L2924/30105 , H01L2924/0665 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor device includes a first semiconductor die. A plurality of conductive vias is formed around the first semiconductor die. A first conductive layer is formed over a first surface of the first semiconductor die and electrically connects to the plurality of conductive vias. A second conductive layer is formed over a second surface of the first semiconductor die opposite the first surface and electrically connects to the plurality of conductive vias. A first passivation layer is formed over the first surface and includes openings that expose the first conductive layer. A second passivation layer is formed over the second surface and includes openings that expose the second conductive layer. Bonding pads are formed within the openings in the first and second passivation layers and are electrically connected to the first and second conductive layers. An interconnect structure is disposed within the openings in the first and second passivation layers.
摘要翻译： 半导体器件包括第一半导体管芯。 在第一半导体管芯周围形成多个导电通孔。 第一导电层形成在第一半导体管芯的第一表面上并电连接到多个导电通孔。 在与第一表面相对的第一半导体管芯的第二表面上形成第二导电层，并电连接到多个导电通孔。 第一钝化层形成在第一表面上并且包括露出第一导电层的开口。 第二钝化层形成在第二表面上并且包括露出第二导电层的开口。 接合焊盘形成在第一和第二钝化层的开口内，并且电连接到第一和第二导电层。 互连结构设置在第一钝化层和第二钝化层中的开口内。
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26.发明申请Semiconductor Device with Optical Sensor and Method of Forming Interconnect Structure on Front and Backside of the Device 有权具有光学传感器的半导体器件和在器件的前面和后面形成互连结构的方法公开(公告)号：US20110049662A1
公开(公告)日：2011-03-03
申请号：US12941683
申请日：2010-11-08
IPC分类号： H01L31/0203
CPC分类号： H01L31/0203 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L24/05 , H01L24/14 , H01L24/17 , H01L24/19 , H01L24/82 , H01L24/96 , H01L27/14618 , H01L27/14625 , H01L31/0232 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/82039 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01061 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/00
摘要： A semiconductor device includes a carrier and semiconductor die having an optically active region. The semiconductor die is mounted to the carrier to form a separation between the carrier and the semiconductor die. The semiconductor device further includes a passivation layer disposed over a surface of the semiconductor die and a glass layer disposed over a surface of the passivation layer. The passivation layer has a clear portion for passage of light to the optically active region of the semiconductor die. The semiconductor device further includes an encapsulant disposed over the carrier within the separation to form an expansion region around a periphery of the semiconductor die, a first via penetrating the expansion region, glass layer, and passivation layer, a second via penetrating the glass layer and passivation layer to expose a contact pad on the semiconductor die, and a conductive material filling the first and second vias.
摘要翻译： 半导体器件包括具有光学活性区域的载流子和半导体管芯。 半导体管芯安装到载体上以形成载体和半导体管芯之间的间隔。 半导体器件还包括设置在半导体管芯的表面上的钝化层和设置在钝化层表面上的玻璃层。 钝化层具有用于将光通过到半导体管芯的光学活性区域的透明部分。 该半导体器件还包括一个密封剂，该密封剂设置在分离器内部的载体上，以形成围绕半导体管芯周围的扩张区域，穿过膨胀区域的第一通孔，玻璃层和钝化层，穿透玻璃层的第二通孔， 钝化层以暴露半导体管芯上的接触焊盘，以及填充第一和第二通孔的导电材料。
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27.发明授权Semiconductor device with optical sensor and method of forming interconnect structure on front and backside of the device 有权具有光学传感器的半导体器件和在器件的前面和后面形成互连结构的方法公开(公告)号：US07851246B2
公开(公告)日：2010-12-14
申请号：US11965160
申请日：2007-12-27
IPC分类号： H01L29/72
CPC分类号： H01L31/0203 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L24/05 , H01L24/14 , H01L24/17 , H01L24/19 , H01L24/82 , H01L24/96 , H01L27/14618 , H01L27/14625 , H01L31/0232 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/82039 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01061 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/00
摘要： A semiconductor package has a semiconductor die with an optically active region which converts light to an electrical signal. An expansion region is formed around the semiconductor die. A through hole via (THV) is formed in the expansion region. Conductive material is deposited in the THV. A passivation layer is formed over the semiconductor die. The passivation layer allows for passage of light to the optically active region of the semiconductor die. A glass layer is applied to the passivation layer. A first RDL is electrically connected between the THV and a contact pad of the semiconductor die. Additional RDLs are formed on a front and back side of the semiconductor die. An under bump metallization (UBM) layer is formed over and electrically connected to the intermediate conduction layer. Solder material is deposited on the UBM and reflowed to form a solder bump.
摘要翻译： 半导体封装具有将光转换成电信号的具有光学有效区域的半导体管芯。 在半导体管芯周围形成扩展区域。 在膨胀区域形成通孔通孔（THV）。 导电材料沉积在THV中。 在半导体管芯上形成钝化层。 钝化层允许光通过半导体管芯的光学活性区域。 玻璃层被施加到钝化层。 第一RDL电连接在THV和半导体管芯的接触焊盘之间。 另外的RDL形成在半导体管芯的前侧和后侧。 在中间导电层之上形成并电连接凹凸金属化（UBM）层。 焊料沉积在UBM上并回流以形成焊料凸点。
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28.发明申请Semiconductor Device with Optical Sensor and Method of Forming Interconnect Structure on Front and Backside of the Device 有权具有光学传感器的半导体器件和在器件的前面和后面形成互连结构的方法公开(公告)号：US20090166785A1
公开(公告)日：2009-07-02
申请号：US11965160
申请日：2007-12-27
IPC分类号： H01L31/0224 , H01L31/18
CPC分类号： H01L31/0203 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L24/05 , H01L24/14 , H01L24/17 , H01L24/19 , H01L24/82 , H01L24/96 , H01L27/14618 , H01L27/14625 , H01L31/0232 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/82039 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01061 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/00
摘要： A semiconductor package has a semiconductor die with an optically active region which converts light to an electrical signal. An expansion region is formed around the semiconductor die. A through hole via (THV) is formed in the expansion region. Conductive material is deposited in the THV. A passivation layer is formed over the semiconductor die. The passivation layer allows for passage of light to the optically active region of the semiconductor die. A glass layer is applied to the passivation layer. A first RDL is electrically connected between the THV and a contact pad of the semiconductor die. Additional RDLs are formed on a front and back side of the semiconductor die. An under bump metallization (UBM) layer is formed over and electrically connected to the intermediate conduction layer. Solder material is deposited on the UBM and reflowed to form a solder bump.
摘要翻译： 半导体封装具有将光转换成电信号的具有光学有效区域的半导体管芯。 在半导体管芯周围形成扩展区域。 在膨胀区域形成通孔通孔（THV）。 导电材料沉积在THV中。 在半导体管芯上形成钝化层。 钝化层允许光通过半导体管芯的光学活性区域。 玻璃层被施加到钝化层。 第一RDL电连接在THV和半导体管芯的接触焊盘之间。 另外的RDL形成在半导体管芯的前侧和后侧。 在中间导电层之上形成并电连接凹凸金属化（UBM）层。 焊料沉积在UBM上并回流以形成焊料凸点。
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29.发明申请Semiconductor Package and Method of Forming Similar Structure for Top and Bottom Bonding Pads 有权用于顶部和底部粘结垫的半导体封装和形成相似结构的方法公开(公告)号：US20090146282A1
公开(公告)日：2009-06-11
申请号：US11952502
申请日：2007-12-07
CPC分类号： H01L23/5389 , H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/4951 , H01L23/49575 , H01L24/16 , H01L24/18 , H01L24/19 , H01L24/81 , H01L24/82 , H01L24/96 , H01L25/0657 , H01L25/105 , H01L2224/04105 , H01L2224/05001 , H01L2224/05008 , H01L2224/05024 , H01L2224/05026 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05569 , H01L2224/05572 , H01L2224/05639 , H01L2224/05644 , H01L2224/05655 , H01L2224/05666 , H01L2224/12105 , H01L2224/16225 , H01L2224/18 , H01L2224/2919 , H01L2224/32225 , H01L2224/73204 , H01L2224/81801 , H01L2225/06524 , H01L2225/1035 , H01L2225/1058 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/19107 , H01L2924/30105 , H01L2924/0665 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor package has a first semiconductor die mounted on a substrate. A conductive via is formed through the substrate. A first RDL is formed on a first surface of the substrate in electrical contact with the conductive via and the first semiconductor die. A second RDL is formed on a second surface of the substrate opposite the first surface of the substrate die in electrical contact with the conductive via. A second semiconductor die can be mounted on the substrate and electrically connected to the second RDL. Bonding pads are formed over the first and second surfaces of the substrate in electrical contact with the first and second RDLs, respectively. The bonding pads on opposite surfaces of the substrate are aligned. Solder bumps or bond wires can be formed on the bonding pads. The semiconductor packages can be stacked and electrically connected through the aligned bonding pads.
摘要翻译： 半导体封装具有安装在基板上的第一半导体管芯。 通过衬底形成导电通孔。 第一RDL形成在与导电通孔和第一半导体管芯电接触的基板的第一表面上。 第二RDL形成在与导电通孔电接触的与衬底管芯的第一表面相对的衬底的第二表面上。 第二半导体管芯可以安装在基板上并电连接到第二RDL。 接合焊盘分别形成在基板的第一和第二表面上，与第一和第二RDL电接触。 对准衬底的相对表面上的接合焊盘。 焊接凸块或接合线可以形成在焊盘上。 半导体封装可以通过对准的焊盘层叠并电连接。
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30.发明授权Semiconductor device with optical sensor and method of forming interconnect structure on front and backside of the device 有权具有光学传感器的半导体器件和在器件的前面和后面形成互连结构的方法公开(公告)号：US08866248B2
公开(公告)日：2014-10-21
申请号：US12941683
申请日：2010-11-08
IPC分类号： H01L29/72 , H01L31/0203 , H01L21/683 , H01L27/146 , H01L21/56 , H01L23/00 , H01L31/0232
CPC分类号： H01L31/0203 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L24/05 , H01L24/14 , H01L24/17 , H01L24/19 , H01L24/82 , H01L24/96 , H01L27/14618 , H01L27/14625 , H01L31/0232 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/82039 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01061 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/00
摘要： A semiconductor device includes a carrier and semiconductor die having an optically active region. The semiconductor die is mounted to the carrier to form a separation between the carrier and the semiconductor die. The semiconductor device further includes a passivation layer disposed over a surface of the semiconductor die and a glass layer disposed over a surface of the passivation layer. The passivation layer has a clear portion for passage of light to the optically active region of the semiconductor die. The semiconductor device further includes an encapsulant disposed over the carrier within the separation to form an expansion region around a periphery of the semiconductor die, a first via penetrating the expansion region, glass layer, and passivation layer, a second via penetrating the glass layer and passivation layer to expose a contact pad on the semiconductor die, and a conductive material filling the first and second vias.
摘要翻译： 半导体器件包括具有光学活性区域的载流子和半导体管芯。 半导体管芯安装到载体上以形成载体和半导体管芯之间的间隔。 半导体器件还包括设置在半导体管芯的表面上的钝化层和设置在钝化层表面上的玻璃层。 钝化层具有用于将光通过到半导体管芯的光学活性区域的透明部分。 该半导体器件还包括一个密封剂，该密封剂设置在分离器内部的载体上，以形成围绕半导体管芯周围的扩张区域，穿过膨胀区域的第一通孔，玻璃层和钝化层，穿透玻璃层的第二通孔和 钝化层以暴露半导体管芯上的接触焊盘，以及填充第一和第二通孔的导电材料。
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