公开(公告)号：US20230418606A1

公开(公告)日：2023-12-28

申请号：US18202161

申请日：2023-05-25

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari

IPC: G06F9/30 ,  G06F15/78 ,  G06F7/60

CPC classification number: G06F9/3004 ,  G06F9/30021 ,  G06F9/30036 ,  G06F15/7839 ,  G06F7/607 ,  G06F15/7821

Abstract: Examples of the present disclosure provide apparatuses and methods for determining a vector population count in a memory. An example method comprises determining, using sensing circuitry, a vector population count of a number of fixed length elements of a vector stored in a memory array.

公开(公告)号：US20230367738A1

公开(公告)日：2023-11-16

申请号：US17741915

申请日：2022-05-11

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： David D. MOSER ,  Daniel L. STANLEY ,  Jennifer KOEHLER ,  Stephen A. CHADWICK

IPC: G06F15/78 ,  H01L29/78

CPC classification number: G06F15/7825 ,  G06F15/7839 ,  H01L29/785 ,  G06F2015/763

Abstract: A logic power network provided in an application-specific integrated circuit (ASIC). The ASIC includes a central processor. The ASIC also includes at least one intellectual property (IP) core operatively connected with the central processor and having a set of electrical components provided therein. The ASIC also includes a network-on-chip (NOC) operatively connected with the central processor and the at least one IP core. The ASIC also includes a logic power network operatively connected with the central processor, the at least one IP core and the set of electrical components therein, and the NOC. The logic power network is adapted to control power of the at least one IP core and the set of electrical components provided in the at least one IP Core individually and separately.

公开(公告)号：US20230195685A1

公开(公告)日：2023-06-22

申请号：US18170900

申请日：2023-02-17

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Shubra Marwaha ,  Ashutosh Garg ,  Supratim Pal ,  Jorge Parra ,  Chandra Gurram ,  Varghese George ,  Darin Starkey ,  Guei-Yuan Lueh

IPC: G06F15/78 ,  G06F9/30 ,  G06F12/128 ,  G06F17/16 ,  G06F12/0811 ,  G06F12/02 ,  G06F12/0866 ,  G06F7/544 ,  G06F9/50 ,  G06F17/18 ,  G06F9/38 ,  G06F12/0891 ,  G06F12/06 ,  G06F12/0888 ,  G06F12/0802 ,  G06T1/60 ,  G06F12/0871 ,  G06T1/20 ,  H03M7/46 ,  G06F12/0875 ,  G06F12/0862 ,  G06F15/80 ,  G06F12/0897 ,  G06F12/0893 ,  G06F12/0804 ,  G06F12/0882 ,  G06F7/575 ,  G06F12/1009 ,  G06F12/0895 ,  G06F7/58 ,  G06T15/06 ,  G06N3/08

CPC classification number: G06F15/7839 ,  G06F9/30043 ,  G06F12/128 ,  G06F17/16 ,  G06F12/0811 ,  G06F12/0238 ,  G06F12/0866 ,  G06F9/30014 ,  G06F7/5443 ,  G06F9/5077 ,  G06F12/0246 ,  G06F17/18 ,  G06F9/3887 ,  G06F12/0891 ,  G06F12/0607 ,  G06F12/0888 ,  G06F12/0802 ,  G06T1/60 ,  G06F9/30079 ,  G06F12/0871 ,  G06F9/30036 ,  G06T1/20 ,  H03M7/46 ,  G06F12/0215 ,  G06F12/0875 ,  G06F12/0862 ,  G06F15/8046 ,  G06F9/30047 ,  G06F9/30065 ,  G06F12/0897 ,  G06F9/5011 ,  G06F12/0893 ,  G06F12/0804 ,  G06F12/0882 ,  G06F9/3001 ,  G06F7/575 ,  G06F12/1009 ,  G06F9/3004 ,  G06F12/0895 ,  G06F7/588 ,  G06F2212/401 ,  G06F2212/1044 ,  G06F9/3867 ,  G06F9/3818 ,  G06F9/3802 ,  G06F2212/455 ,  G06F2212/1021 ,  G06F2212/60 ,  G06F2212/1008 ,  G06T15/06 ,  G06N3/08 ,  G06F2212/302

Abstract: Described herein is a graphics processing unit (GPU) configured to receive an instruction having multiple operands, where the instruction is a single instruction multiple data (SIMD) instruction configured to use a bfloat16 (BF16) number format and the BF16 number format is a sixteen-bit floating point format having an eight-bit exponent. The GPU can process the instruction using the multiple operands, where to process the instruction includes to perform a multiply operation, perform an addition to a result of the multiply operation, and apply a rectified linear unit function to a result of the addition.

公开(公告)号：US20190243653A1

公开(公告)日：2019-08-08

申请号：US16226508

申请日：2018-12-19

Applicant: Cavium, LLC

Inventor： Avinash SODANI ,  Ulf HANEBUTTE ,  Senad DURAKOVIC ,  Hamid Reza GHASEMI ,  Chia-Hsin CHEN

IPC: G06F9/38 ,  G06N5/04 ,  G06N20/00

CPC classification number: G06N20/00 ,  G06F9/3802 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/544 ,  G06F12/063 ,  G06F12/0862 ,  G06F15/7807 ,  G06F15/7839 ,  G06F17/16 ,  G06F2212/602 ,  G06N3/063 ,  G06N5/04 ,  G06N20/10

Abstract: A programmable hardware system for machine learning (ML) includes a core and an inference engine. The core receives commands from a host. The commands are in a first instruction set architecture (ISA) format. The core divides the commands into a first set for performance-critical operations, in the first ISA format, and a second set of performance non-critical operations, in the first ISA format. The core executes the second set to perform the performance non-critical operations of the ML operations and streams the first set to inference engine. The inference engine generates a stream of the first set of commands in a second ISA format based on the first set of commands in the first ISA format. The first set of commands in the second ISA format programs components within the inference engine to execute the ML operations to infer data.

公开(公告)号：US20180342021A1

公开(公告)日：2018-11-29

申请号：US15607577

申请日：2017-05-29

Applicant: Virtual OnQ Systems, LLC

Inventor： Gokhan Gulec

IPC: G06Q50/12 ,  G06F3/16 ,  G06F15/78 ,  G10L15/22 ,  G07C1/10

CPC classification number: G06Q50/12 ,  G06F3/167 ,  G06F15/7839 ,  G07C1/10 ,  G07C9/00158 ,  G07C9/00166 ,  G07C9/00904 ,  G10L2015/223 ,  G10L2015/225

Abstract: A method for voice activated hotel room monitoring includes transmitting to a mobile number from a voice driven computer assistant disposed within a room of a hotel, a message inviting registration of a guest assigned to the room. In response to a registration of the guest received from the number, a unique identifier is assigned to the guest, a record is stored in a registry that associates the guest with the identifier and the room, and the identifier is transmitted to the mobile number. Thereafter, a voice command is detected in the assistant and, in response, the command is speech recognized into text and parsed to locate the identifier. Then, the registry is queried with the identifier. In the event that the identifier corresponds to the guest assigned to the room, a directive in the text is processed in connection with a service offered to the guest by the hotel.

公开(公告)号：US20180267807A1

公开(公告)日：2018-09-20

申请号：US15595582

申请日：2017-05-15

Applicant: Microsoft Technology Licensing, LLC

Inventor： Douglas C. Burger ,  Gagan Gupta

IPC: G06F9/38 ,  G06F9/48 ,  G06F15/78

CPC classification number: G06F9/3861 ,  G06F9/30116 ,  G06F9/3832 ,  G06F9/3836 ,  G06F9/3859 ,  G06F9/3863 ,  G06F9/3865 ,  G06F9/4806 ,  G06F9/4812 ,  G06F15/76 ,  G06F15/7839 ,  G06F2209/481

Abstract: Systems and methods are disclosed for supporting debugging of programs in block-based processor architectures. In one example of the disclosed technology, a processor includes an exception event handler, a memory interface, at least one block-based processor core coupled to the memory interface and configured to responsive to receiving an exception event signal while executing an instruction block, store state data for the core generated by executing the instruction block, transfer control of the core to a second instruction block, and resume execution of the first instruction by restoring state for the processor core from the stored state data.

公开(公告)号：US09959246B2

公开(公告)日：2018-05-01

申请号：US14728522

申请日：2015-06-02

Applicant: Optimum Semiconductor Technologies, Inc.

Inventor： Mayan Moudgill ,  C. John Glossner ,  Arthur Joseph Hoane ,  Paul Hurtley ,  Vitaly Kalashnikov

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/78 ,  G06F15/80 ,  G06F17/14

CPC classification number: G06F15/8053 ,  G06F9/3001 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30141 ,  G06F9/3836 ,  G06F9/3855 ,  G06F15/7828 ,  G06F15/7839 ,  G06F15/8076 ,  G06F17/142

Abstract: A computer processor is disclosed. The computer processor may comprise a vector unit comprising a vector register file comprising one or more registers to hold a varying number of elements. The computer processor may further comprise processing logic configured to implicitly type each of the varying number of elements in the vector register file. The computer processor may be implemented as a monolithic integrated circuit.

公开(公告)号：US20180113839A1

公开(公告)日：2018-04-26

申请号：US15334398

申请日：2016-10-26

Applicant: Wisconsin Alumni Research Foundation

Inventor： Jing Li ,  Soroosh Khoram

IPC: G06F15/78

CPC classification number: G06F15/7839 ,  G06F7/38 ,  G06F15/7821

Abstract: An associative processor separates the arithmetic operation of addition from the carry process to pre-compute contingent carries before the addition which then allows improved parallelism in the addition process. A portion of the contingent carry computation may also be conducted in parallel. The result is higher-speed operations resulting from increased parallelism.

公开(公告)号：US20180047027A1

公开(公告)日：2018-02-15

申请号：US15672880

申请日：2017-08-09

Applicant: FUJITSU LIMITED

Inventor： Tetsuharu Sakurai ,  Shingo Suzuki

IPC: G06Q20/42 ,  G06Q20/38 ,  G06Q20/40 ,  G06Q20/08

CPC classification number: G06Q20/42 ,  G06F15/7839 ,  G06Q20/085 ,  G06Q20/389 ,  G06Q20/40 ,  G06Q20/4037 ,  G06Q20/405

Abstract: A device includes, a memory configured to store a limit value, a first unit value, a first remaining period, and a first usage value, and a processor coupled to the memory and the processor configured, to determine a first multiplication value of the first unit value and the first remaining period, to determine a first addition value of the first multiplication value and the first usage value, to perform a first comparison of the first addition value and the limit value, to perform a determination of whether it is necessary to output a first alert based on the first comparison, the first alert being with respect to the usage of the one or more services, and to output the first alert to a terminal when the determination indicates that it is necessary to output the first alert.

公开(公告)号：US20170351641A1

公开(公告)日：2017-12-07

申请号：US15490743

申请日：2017-04-18

Applicant: Intel Corporation

Inventor： ZEEV SPERBER ,  ROBERT VALENTINE ,  SHLOMO RAIKIN ,  STANISLAV SHWARTSMAN ,  GAL OFIR ,  IGOR YANOVER ,  GUY PATKIN ,  OFER LEVY

IPC: G06F15/78 ,  G06F9/345 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F15/7839 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/3808 ,  G06F9/383

Abstract: Methods and apparatus are disclosed using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode scatter/gather instructions and generate micro-operations. An index array holds a set of indices and a corresponding set of mask elements. A finite state machine facilitates the scatter operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. Storage is allocated in a buffer for each of the set of addresses being generated. Data elements corresponding to the set of addresses being generated are copied to the buffer. Addresses from the set are accessed to store data elements if a corresponding mask element has said first value and the mask element is changed to a second value responsive to completion of their respective stores.