公开(公告)号：US5274482A

公开(公告)日：1993-12-28

申请号：US796248

申请日：1991-11-21

Applicant: Hiroshi Morita ,  Keiko Sunohara ,  Kazunari Nishimura

Inventor： Hiroshi Morita ,  Keiko Sunohara ,  Kazunari Nishimura

IPC: G02F1/1365 ,  G02F1/1343 ,  H01L27/02 ,  H01L29/46 ,  H01L29/88

CPC classification number: G02F1/1365

Abstract: According to the present invention, there is provided a matrix array substrate for a liquid crystal display device comprising a transparent substrate, a plurality of picture element electrodes formed on said transparent substrate and made of a transparent conductive material, and non-linear resistive devices formed on said transparent substrate, and each connected to each of the picture element electrodes. Each of said non-linear resistive devices includes a Ta first electrode formed on said transparent substrate, a second electrode, and an insulating layer located between the first and second electrodes, and the first electrode is connected to another non-linear resistive device via a Ta interconnecting layer. Further, a transparent conductive layer is formed between said transparent substrate and interconnecting layer and is not formed between the transparent substrate and the first electrode.

公开(公告)号：US5258643A

公开(公告)日：1993-11-02

申请号：US735427

申请日：1991-07-25

Applicant: Simon S. Cohen

Inventor： Simon S. Cohen

IPC: H01L23/525 ,  H01L29/34 ,  H01L23/48 ,  H01L29/46 ,  H01L29/54

CPC classification number: H01L23/5252 ,  H01L2924/0002

Abstract: Methods and systems are disclosed for fabricating electrically programmable link structures by fabricating a first conductor, which comprises a refractory conductive material, then fabricating an insulative link material over the refractory conductive material and, subsequently, depositing an upper conductive material over the link material. In use, an electrical path can be formed between the first and second conductive elements by applying a voltage between such elements across at least one selected region of the insulator, such that the insulative link material is transformed in the region and rendered conductive to form an electrical signal path. The link material is preferably a silicon oxide insulator andThe U.S. Government has rights in this invention pursuant to Contract No. F19628-90-C-0002 awarded by the Department of the Air Force.

Abstract translation: 公开了用于制造电可编程链接结构的方法和系统，该方法和系统通过制造包括耐火导电材料的第一导体，然后在耐火导电材料上方制造绝缘连接材料，以及随后在该连接材料上沉积上导电材料。 在使用中，可以在第一和第二导电元件之间通过在绝缘体的至少一个选定区域上的这些元件之间施加电压而形成电路径，使得绝缘链路材料在该区域中变换并导通以形成 电信号路径。 连接材料优选是氧化硅绝缘体，并且还可以包括一个或多个保护性阻挡层，以将氧化物与上部和下部导电元件物理分离。 氮化物特别用作保护性阻挡层。

公开(公告)号：US5252855A

公开(公告)日：1993-10-12

申请号：US775549

申请日：1991-10-15

Applicant: Yoshiaki Ogawa ,  Hiroyuki Noguchi

Inventor： Yoshiaki Ogawa ,  Hiroyuki Noguchi

IPC: H01L23/50 ,  H01L23/495 ,  H05K3/20 ,  H05K3/38 ,  H01L23/48 ,  H01L29/44 ,  H01L29/46 ,  H01L39/02

CPC classification number: H01L23/49506 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H05K3/202 ,  H05K3/385

Abstract: Lead frames, in which at least one part of the surface of a metal member which is a part of the lead frame is provided with an anodic oxide film of copper or a copper alloy, and in which a member composed substantially of a resin film or a resin plate is connected to the lead frame through this anodic oxide film by gluing or pressing under heat exhibit good adhesion between the metal member and the resin film or plate. Similarly, lead frames constructed with at least two metal members, having a portion of the surface provided with an anodic oxide film of copper or a copper alloy, and in which these metal members are joined together through this anodic oxide film exhibit good adhesion between the metal members.

Abstract translation: 引线框架，其中作为引线框架的一部分的金属构件的表面的至少一部分设置有铜或铜合金的阳极氧化膜，并且其中基本上由树脂膜构成的构件或 树脂板通过这种阳极氧化膜通过粘合或加压在金属构件和树脂膜或板之间显示出良好的粘附性而与引线框架连接。 类似地，由至少两个金属构件构成的引线框架，其具有设置有铜或铜合金的阳极氧化膜的表面的一部分，并且其中这些金属构件通过该阳极氧化膜连接在一起，表现出良好的粘附力 金属成员。

公开(公告)号：US4795722A

公开(公告)日：1989-01-03

申请号：US10937

申请日：1987-02-05

Applicant: Michael T. Welch ,  Ronald E. McMann ,  Manuel L. Torreno, Jr. ,  Evaristo Garcia, Jr. ,  Jeffrey E. Brighton

Inventor： Michael T. Welch ,  Ronald E. McMann ,  Manuel L. Torreno, Jr. ,  Evaristo Garcia, Jr. ,  Jeffrey E. Brighton

IPC: H01L21/3205 ,  H01L21/768 ,  H01L21/90 ,  H01L23/48 ,  H01L29/46

CPC classification number: H01L21/76877 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76819 ,  Y10S148/011 ,  Y10S148/043 ,  Y10S148/133 ,  Y10S148/147

Abstract: A method for planarizing a semiconductor slice prior to its metallization is disclosed. The semiconductor slice is processed so as to form the diffusions and underlying interconnection layers using well known techniques. After the deposition and patterning of the last interconnection layer prior to metallization, a layer of the platinum or another metal is deposited onto the slice. The slice is sintered to form a silicide film on those portions of the interconnection layers and diffusions which were directly exposed to the sputtered platinum. A layer of phosphorous-doped dielectric is then deposited, followed by a layer of undoped oxide. Photoresist or another conformal material is spun on to the slice, resulting in a planar top surface. The slice is exposed to a plasma etch which etches both the photoresist and the undoped oxide, resulting in a top surface of the undoped oxide which is substantially planar. Contact vias are etched through the undoped and doped oxides; the silicide film acts as an etch stop, allowing contacts of differing depths to be etched from the planar top surface of the undoped oxide without etching through any of the polysilicon layers to which contact is to be made. A metal such as tungsten is deposited onto the slice to fill the contact vias, and is planarized in the same fashion as was the undoped oxide. The metallization is then sputtered onto the planar surface presented by the planarized undoped oxide and the planarized tungsten, and is patterned and etched to form the desired interconnection pattern.

Abstract translation: 公开了一种在其金属化之前对半导体薄片进行平坦化的方法。 处理半导体片以便使用公知的技术形成扩散和下面的互连层。 在金属化之前沉积和图案化最后的互连层之后，将铂或另一种金属层沉积在切片上。 将切片烧结以在直接暴露于溅射铂的互连层和扩散部分上形成硅化物膜。 然后沉积一层磷掺杂电介质，随后是一层未掺杂的氧化物。 将光致抗蚀剂或其他保形材料旋转到切片上，得到平坦的顶表面。 将切片暴露于等离子体蚀刻，其蚀刻光致抗蚀剂和未掺杂的氧化物，导致基本上为平面的未掺杂氧化物的顶表面。 接触孔通过未掺杂和掺杂的氧化物蚀刻; 硅化物膜用作蚀刻停止件，允许从未掺杂的氧化物的平坦顶表面蚀刻不同深度的接触，而不蚀刻通过要进行接触的任何多晶硅层。 将诸如钨的金属沉积在切片上以填充接触孔，并且以与未掺杂的氧化物相同的方式被平坦化。 然后将金属化溅射到由平坦化未掺杂的氧化物和平坦化钨呈现的平坦表面上，并被图案化和蚀刻以形成所需的互连图案。

公开(公告)号：US4635091A

公开(公告)日：1987-01-06

申请号：US639642

申请日：1984-08-10

Applicant: Bernard P. Roger

Inventor： Bernard P. Roger

IPC: H01L23/58 ,  H01L23/485 ,  H01L23/532 ,  H01L23/62 ,  H01L23/48 ,  H01L27/02 ,  H01L29/46 ,  H01L29/62

CPC classification number: H01L24/05 ,  H01L23/53219 ,  H01L23/62 ,  H01L24/48 ,  H01H2085/0275 ,  H01H2085/0283 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05073 ,  H01L2224/05617 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/4847 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01051 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/14

Abstract: The transistor includes a semiconductor body having a surface on which are disposed metallic connection contact areas, including means for protection from overloads. At least one of the metallic area comprises a material, such as Al, susceptible to forming a eutectic with the substrate, which is made, for example, of Si. The metallic area is formed from an alloy of the material, such as the Al-Si eutectic, having a melting point whose temperature is lower than the formation temperature of the Al-Si eutectic and higher than the temperature of soldering the semiconductor body on a support.

Abstract translation: 晶体管包括半导体本体，其表面上设有金属连接接触区域，包括用于防止过载的装置。 金属区域中的至少一个包括易于与衬底形成共晶的诸如Al的材料，其由例如Si制成。 金属区域由Al-Si共晶体材料的合金形成，Al-Si共晶体的熔点温度低于Al-Si共晶体的形成温度，并且高于在半导体本体上的焊接温度 支持。

公开(公告)号：US4581627A

公开(公告)日：1986-04-08

申请号：US459187

申请日：1983-01-19

Applicant: Yoshiya Ueda ,  Fumie Okutsu ,  Masaki Momotomi

Inventor： Yoshiya Ueda ,  Fumie Okutsu ,  Masaki Momotomi

IPC: H01L21/28 ,  H01L21/3205 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L27/12 ,  H01L23/48 ,  H01L29/46 ,  H01L29/54

CPC classification number: H01L21/28167 ,  H01L21/28097 ,  H01L21/28176 ,  H01L21/32053 ,  H01L29/49 ,  H01L29/4975 ,  H01L21/28211 ,  H01L29/51 ,  H01L2924/0002 ,  Y10S148/083 ,  Y10S148/14

Abstract: The invention provides a semiconductor device in which an insulating film or a semiconductor film is firmly bonded with a metal silicide film, and also provides a method for manufacturing the same. The semiconductor device has a semiconductor substrate with an insulating film or a semiconductor film formed thereon, a carbon layer formed on the insulating film or the semiconductor film, and a metal silicide film formed on the carbon layer. Carbon atoms are thermally diffused by heating from the carbon layer into the insulating film or the semiconductor film and into the metal silicide film.

Abstract translation: 本发明提供一种半导体器件，其中绝缘膜或半导体膜与金属硅化物膜牢固地接合，并且还提供其制造方法。 半导体器件具有在其上形成有绝缘膜或半导体膜的半导体衬底，形成在绝缘膜或半导体膜上的碳层和形成在碳层上的金属硅化物膜。 碳原子通过从碳层加热到绝缘膜或半导体膜中并进入金属硅化物膜而热扩散。

公开(公告)号：US4511634A

公开(公告)日：1985-04-16

申请号：US354467

申请日：1982-03-03

Applicant: Friedrich W. Nickol

Inventor： Friedrich W. Nickol

IPC: B23K1/20 ,  B23K35/00 ,  B23K35/14 ,  G02F1/1345 ,  H05K3/28 ,  H01L23/48 ,  H01L29/46

CPC classification number: H05K3/282 ,  B23K1/20 ,  B23K35/001 ,  G02F1/1345 ,  H05K2201/0326 ,  Y10S428/929 ,  Y10T428/12542 ,  Y10T428/12549 ,  Y10T428/1259 ,  Y10T428/12611 ,  Y10T428/12618 ,  Y10T428/1266 ,  Y10T428/12681 ,  Y10T428/12708 ,  Y10T428/12715 ,  Y10T428/12722 ,  Y10T428/12736 ,  Y10T428/12743 ,  Y10T428/1275 ,  Y10T428/12757 ,  Y10T428/12764 ,  Y10T428/12806 ,  Y10T428/12812 ,  Y10T428/12847 ,  Y10T428/12986

Abstract: The invention refers to a corrosion-proof solderable system of layers which is applied to a support and is made of a solderable layer and a corrosion-protection layer covering the solderable layer and protecting it from complete oxidation. In order to create a layer system which is simpler and cheaper to manufacture, the solderable layer contains a proportion of oxidizable metal.The corrosion-protection layer is made by oxidation of the solderable layer on its free surface.

Abstract translation: 本发明涉及一种耐腐蚀可焊接层系统，其被施加到支撑体上，并且由可焊层和覆盖可焊层的防腐层制成，并防止其完全氧化。 为了形成制造简单且便宜的层系，可焊层含有一定比例的可氧化金属。 防腐层由可焊层自由表面氧化制成。

公开(公告)号：US4445134A

公开(公告)日：1984-04-24

申请号：US318181

申请日：1981-11-04

Applicant: Robert J. Miller

Inventor： Robert J. Miller

IPC: H01L21/285 ,  H01L29/45 ,  H01L29/49 ,  H01L23/48 ,  H01L29/46 ,  H01L29/62 ,  H01L29/64

CPC classification number: H01L29/4966 ,  H01L21/28518 ,  H01L29/456 ,  H01L29/4975

Abstract: A highly conductive layer utilizing a layer of Pt in conjunction with sputter deposited or co-evaporated WSi.sub.2 to enhance the conductivity increase of the WSi.sub.2 layer occuring during annealing. The Pt layer is deposited as a thin layer directly on top or beneath the WSi.sub.2 layer or may be incorporated within the WSi.sub.2 layer. During annealing platinum atoms diffuse into the WSi.sub.2 film resulting in lower resistivity values than in comparably deposited annealed film wherein the Pt layer has been omitted.

Abstract translation: 使用Pt层与溅射沉积或共蒸发WSi2结合的高导电层，以增强退火过程中发生的WSi2层的电导率增加。 Pt层作为薄层直接沉积在WSi2层的上面或下面，或者可以并入WSi2层内。 在铂退火退火过程中，铂原子扩散到WSi2膜中，导致电阻率值低于相对沉积的退火膜，其中Pt层已被省略。

公开(公告)号：US4358784A

公开(公告)日：1982-11-09

申请号：US98850

申请日：1979-11-30

Applicant: Joseph Wislocky ,  Thomas J. Roach

Inventor： Joseph Wislocky ,  Thomas J. Roach

IPC: H01L21/60 ,  H01L23/492 ,  H01L23/48 ,  H01L29/46 ,  H01L29/54

CPC classification number: H01L24/33 ,  H01L23/4924 ,  H01L24/28 ,  H01L24/83 ,  H01L2224/04026 ,  H01L2224/8319 ,  H01L2224/83801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12036

Abstract: An alloyed diode is formed of a silicon wafer which is sandwiched between two pre-clad molybdenum disks. The upper molybdenum disk is clad on the side facing the silicon wafer with a thin aluminum foil and is clad on its outer surface with a nickel foil. The bottom molybdenum is clad with a solder foil of silver containing small amounts of germanium, copper and arsenic on the surface facing the silicon and is clad with nickel on its opposite surface. The three parts are stacked atop one another and placed in an alloying furnace to form a completed semiconductor wafer with solderable electrodes on opposite sides.

Abstract translation: 合金二极管由夹在两个预包层钼盘之间的硅晶片形成。 上钼盘用薄铝箔包覆在面向硅晶片的一侧，并用镍箔包覆在其外表面上。 底部的钼包覆有在面向硅的表面上含有少量锗，铜和砷的银的焊锡箔，并在其相对表面上用镍包覆。 将这三个部件彼此堆叠放置在合金炉中，以在相对的两侧形成具有可焊接电极的完整的半导体晶片。

公开(公告)号：US4224115A

公开(公告)日：1980-09-23

申请号：US919308

申请日：1978-06-26

Applicant: Aiichiro Nara ,  Hisao Kondo ,  Takeji Fujiwara ,  Hideaki Ikegawa

Inventor： Aiichiro Nara ,  Hisao Kondo ,  Takeji Fujiwara ,  Hideaki Ikegawa

IPC: H01L21/288 ,  C25D5/02 ,  C25D7/12 ,  H01L29/46

CPC classification number: H01L21/2885

Abstract: Semiconductor substrates electroplated with nickel-palladium alloy consisting of above 50 to 80 atomic percent nickel and below 50 to 20 atomic percent palladium exhibit excellent thermal stability.

Abstract translation: 用镍 - 钯合金电镀镍基合金和半导体衬底，镍 - 钯合金由50〜80原子％的镍和50〜20原子％的钯组成，具有优异的热稳定性。