公开(公告)号：US11984512B2

公开(公告)日：2024-05-14

申请号：US17033444

申请日：2020-09-25

申请人： Intel Corporation

发明人： Uri Bear ,  Elad Peer ,  Elena Sidorov ,  Rami Sudai ,  Reuven Elbaum ,  Steve J. Brown

IPC分类号： H01L29/788 ,  G11C16/04 ,  H01L29/423 ,  H01L29/66 ,  H10B41/00 ,  H10B43/00

CPC分类号： H01L29/788 ,  G11C16/0408 ,  H01L29/42324 ,  H01L29/66825 ,  H10B41/00 ,  H10B43/00

摘要： In one embodiment, memory cell includes a control gate, a floating gate, a substrate comprising a source region and a drain region, a first isolator between the control gate and floating gate, and a second isolator between the floating gate and the substrate. The memory cell is configured to have a retention time that is within a statistical window around a selected lifespan. The selected lifespan may be less than ten years, such as, for example, less than one year, less than one month, or less than one week.

公开(公告)号：US11983622B2

公开(公告)日：2024-05-14

申请号：US18111471

申请日：2023-02-17

申请人： Samsung Electronics Co., Ltd.

发明人： Borna J. Obradovic ,  Titash Rakshit ,  Mark S. Rodder

IPC分类号： G06N3/065 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/808 ,  H10B41/30

CPC分类号： G06N3/065 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/8083 ,  H10B41/30

摘要： A neuromorphic device for the analog computation of a linear combination of input signals, for use, for example, in an artificial neuron. The neuromorphic device provides non-volatile programming of the weights, and fast evaluation and programming, and is suitable for fabrication at high density as part of a plurality of neuromorphic devices. The neuromorphic device is implemented as a vertical stack of flash-like cells with a common control gate contact and individually contacted source-drain (SD) regions. The vertical stacking of the cells enables efficient use of layout resources.

公开(公告)号：US11980031B2

公开(公告)日：2024-05-07

申请号：US17128915

申请日：2020-12-21

申请人： Kioxia Corporation

发明人： Takashi Ishida ,  Yoshiaki Fukuzumi ,  Takayuki Okada ,  Masaki Tsuji

IPC分类号： H01L29/792 ,  H01L21/336 ,  H01L27/115 ,  H01L29/10 ,  H01L29/423 ,  H01L29/788 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC分类号： H10B43/27 ,  H01L29/1037 ,  H01L29/4234 ,  H10B43/10 ,  H10B43/35

摘要： According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.

公开(公告)号：US11968830B2

公开(公告)日：2024-04-23

申请号：US18178527

申请日：2023-03-05

申请人： Winbond Electronics Corp.

发明人： Chung-Hsuan Wang

IPC分类号： H01L21/00 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H10B41/30 ,  H10B41/42

CPC分类号： H10B41/42 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883 ,  H10B41/30

摘要： Provided is a method of manufacturing a memory device and a patterning method. The patterning method includes following steps. A control structure including stop layers and oxide layers stacked alternately, a hard mask layer, and a mask pattern are sequentially formed on a target layer. A photoresist layer is formed in the mask pattern on the hard mask layer. A portion of the hard mask layer and a portion of the control structure are removed to form first openings by using the photoresist layer and the mask pattern as a mask. The photoresist layer and the hard mask layer are removed to form a second opening having a bottom surface higher than that of the first openings. At least one etching process is performed so that the first and second openings extend into and divide the control structure and the target layer into stack structures.

公开(公告)号：US11968829B2

公开(公告)日：2024-04-23

申请号：US17834746

申请日：2022-06-07

申请人： Silicon Storage Technology, Inc.

发明人： Zhuoqiang Jia ,  Leo Xing ,  Xian Liu ,  Serguei Jourba ,  Nhan Do

IPC分类号： H10B41/42 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788

CPC分类号： H10B41/42 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

摘要： A method includes recessing an upper surface of a substrate in first and second areas relative to a third area, forming a first conductive layer in the first area, forming a second conductive layer in the three areas, selectively removing the first and second conductive layers in the first area, while maintaining the second conductive layer in the second and third areas, leaving pairs of stack structures in the first area respectively having a control gate of the second conductive layer and a floating gate of the first conductive layer, forming a third conductive layer in the three areas, recessing the upper surface of the third conductive layer below tops of the stack structures and removing the third conductive layer from the second and third areas, removing the second conductive layer from the second and third areas, and forming blocks of metal material in the second and third areas.

公开(公告)号：US11950412B2

公开(公告)日：2024-04-02

申请号：US17670975

申请日：2022-02-14

申请人： LONGITUDE FLASH MEMORY SOLUTIONS LTD.

发明人： Youseok Suh ,  Sung-Yong Chung ,  Ya-Fen Lin ,  Yi-Ching Jean Wu

IPC分类号： H01L29/788 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H10B41/30 ,  H10B41/35 ,  H10B43/30 ,  H10B43/35

CPC分类号： H10B41/35 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792 ,  H10B41/30 ,  H10B43/30 ,  H10B43/35

摘要： A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select transistor coupled to a second end of the string of memory transistor. Each memory transistor includes a gate electrode formed adjacent to a charge trapping layer and there is neither a source nor a drain junction between adjacent pairs of memory transistors or between the memory transistors and source select transistor or drain select transistor. In one embodiment, the memory transistors are spaced apart from adjacent memory transistors and the source select transistor and drain select transistor, such that channels are formed therebetween based on a gate fringing effect associated with the memory transistors. Other embodiments are also described.

公开(公告)号：US11949022B2

公开(公告)日：2024-04-02

申请号：US17678971

申请日：2022-02-23

申请人： Micron Technology, Inc.

发明人： Zhenyu Lu ,  Hongbin Zhu ,  Gordon A. Haller ,  Roger W. Lindsay ,  Andrew Bicksler ,  Brian J. Cleereman ,  Minsoo Lee

IPC分类号： H01L29/788 ,  H01L21/285 ,  H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

CPC分类号： H01L29/788 ,  H01L21/28518 ,  H01L23/535 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

摘要： A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.

公开(公告)号：US11908953B2

公开(公告)日：2024-02-20

申请号：US18081703

申请日：2022-12-15

申请人： Winbond Electronics Corp.

发明人： Che-Jui Hsu ,  Ying-Fu Tung ,  Chun-Sheng Lu ,  Kuo-Feng Huang ,  Yu-Chi Kuo ,  Wang-Ta Li

IPC分类号： H01L29/788 ,  H01L21/26 ,  H01L29/66 ,  H10B41/35

CPC分类号： H01L29/788 ,  H01L29/66825 ,  H10B41/35

摘要： A manufacturing method of a memory device are provided. The method includes following steps. A gate stacking structure is formed over a substrate. A first insulating layer, a second insulating layer and a mask material layer are sequentially formed over the substrate to cover the gate stacking structure. An ion implantation process is performed on the mask material layer to form a doped portion in the mask material layer. The doped portion caps on a top portion of the gate stacking structure. A first patterning process is performed on the mask material layer using the doped portion as a shadow mask to remove a bottom portion of the mask material layer extending along a surface of the substrate. A second patterning process is performed to remove the doped portion of the mask material layer and an exposed bottom portion of the second insulating layer surrounding the gate stacking structure.

公开(公告)号：US11908889B2

公开(公告)日：2024-02-20

申请号：US17428137

申请日：2019-12-05

申请人： SUZHOU ORIENTAL SEMICONDUCTOR CO., LTD.

发明人： Yi Gong ,  Wei Liu ,  Yuanlin Yuan ,  Lei Liu ,  Rui Wang

IPC分类号： H01L29/06 ,  H01L27/06 ,  H01L29/88 ,  H01L29/78 ,  H01L29/788

CPC分类号： H01L29/0634 ,  H01L27/0629 ,  H01L29/788

摘要： Provided is a semiconductor super junction power device. The semiconductor super junction power device includes an MOSFET cell array composed of multiple super junction MOSFET cells. Each of multiple MOSFET cells includes a p-type body region located at the top of an n-type drift region, a p-type columnar doping region located below the p-type body region, an n-type source region located in the p-type body region, a gate dielectric layer located above the p-type body region, a gate electrode located above the p-type body region, an n-type floating gate located above the p-type body region and an opening located in the gate dielectric layer, where in a lateral direction, the gate electrode is located on one side close to the n-type source region; an opening located in the gate dielectric layer, where the n-type floating gate contacts the p-type body region through the opening to form a p-n junction diode.

公开(公告)号：US20240049463A1

公开(公告)日：2024-02-08

申请号：US18487546

申请日：2023-10-16

申请人： KEY FOUNDRY CO., LTD.

发明人： Su Jin KIM ,  Min Kuck CHO ,  Jung Hwan LEE ,  In Chul JUNG

IPC分类号： H10B41/35 ,  H01L29/66 ,  H01L29/788

CPC分类号： H10B41/35 ,  H01L29/66825 ,  H01L29/7883

摘要： A single poly non-volatile memory device is provided. The single poly non-volatile memory device is formed in a semiconductor substrate, and includes a sensing transistor, a selection transistor, and a capacitor, wherein a thickness of a selection gate insulating film is formed to be thicker than a thickness of a sensing gate insulating film, wherein a thickness of a control gate insulating film of the capacitor is formed to be the same, or greater than, a thickness of the sensing gate insulating film, and wherein the sensing gate of the sensing transistor and the control gate of the capacitor are physically and electrically connected to each other.