公开(公告)号：US09825044B2

公开(公告)日：2017-11-21

申请号：US15289161

申请日：2016-10-08

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Balasubramanian Pranatharthiharan ,  Hui Zang

IPC: H01L21/76 ,  H01L27/11 ,  H01L21/02 ,  H01L29/08 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L27/1104 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/3043 ,  H01L21/324 ,  H01L21/76 ,  H01L21/76224 ,  H01L21/8221 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/1116 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: The method for preventing epitaxial growth in a semiconductor device begins with cutting a set of long fins into a set of fins of a FinFET structure, the set of fins having respective cut faces of a set of cut faces located at respective fin ends of a set of fin ends. A photoresist layer is patterned over the set of fin ends of the set of fins of the FinFET structure. The photoresist pattern over the set of fin ends differs from the photoresist pattern over other areas of the FinFET structure as the photoresist pattern over the set of fin ends protects the first dielectric material at the set of fin ends. A set of dielectric blocks is formed at the set of fin ends, wherein each of the dielectric blocks covers at least one cut face. The set of dielectric blocks prevents epitaxial growth at the set of fin ends in a subsequent epitaxial growth step.

公开(公告)号：US09824748B1

公开(公告)日：2017-11-21

申请号：US15395036

申请日：2016-12-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Manfred Eller ,  Min-hwa Chi

IPC: G11C11/00 ,  H01L27/088 ,  H01L21/8238 ,  G11C11/412 ,  H01L27/11 ,  H01L29/10 ,  H01L29/06 ,  H01L29/49 ,  G11C11/419 ,  H01L27/12 ,  H01L21/84 ,  H01L21/762 ,  H01L27/02 ,  H01L27/092

CPC classification number: G11C11/412 ,  G11C11/4125 ,  G11C11/419 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/0928 ,  H01L27/1104 ,  H01L27/1203 ,  H01L29/0649

Abstract: Static random access memory (SRAM) bitcell structures with improved minimum operation voltage (Vmin) and yield are provided. The structures may include a silicon substrate, a deep n-well (DNW) layer, p-well (PW) regions, doped back-plate (BP) regions, a buried oxide (BOX) layer, and/or active regions formed on the BOX layer and over portions of the BP regions. At least one BP region may extend below at least one shallow trench isolation (STI) region, at least one contact to back plate (CBP), at least one active region and at least one PC construct overlapping the at least one active region forming a channel of at least one of a first pull-up (PU1) transistor and a second pull-up (PU2) transistor. The at least one CBP facilitates biasing of at least one the PU1 and PU2 transistors during at least one of a read, write or standby operation of the structures.

公开(公告)号：US09805982B1

公开(公告)日：2017-10-31

申请号：US15156767

申请日：2016-05-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi ,  Jinping Liu

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/49

CPC classification number: H01L21/823456 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/4916 ,  H01L29/6653 ,  H01L29/66545

Abstract: A method of adjusting work-function metal thickness includes providing a structure having a substrate, the substrate including a longitudinally extending array of fins disposed thereon. Spacers are then formed on sidewalls of fins of the array. Pillars are formed between and adjacent the spacers. A gate having dummy gate material is formed over the structure, the gate extending laterally across the spacers and fins of the array. The dummy gate material and spacers are removed from the gate to form work-function (WF) metal trenches defined by the pillars and fins within the gate. The WF metal trenches have a first trench width. A thickness of the pillars is adjusted to provide a second trench width, different from the first trench width, for the WF metal trenches. A WF metal structure is disposed within the WF metal trenches.

公开(公告)号：US09799514B1

公开(公告)日：2017-10-24

申请号：US15093292

申请日：2016-04-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi

IPC: H01L21/22 ,  H01L21/033 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/02238 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823475

Abstract: A method includes, for example, a starting semiconductor structure comprising a plurality of material lines disposed over a hard mask, and the hard mask disposed over a patternable layer, forming a first protective layer over some of the plurality of material lines, the protected material lines and the unprotected material lines having a same corresponding first critical dimension, oxidizing the unprotected material lines so that the oxidized unprotected material lines have an increased second critical dimension greater than the first critical dimension, removing the first protective layer, forming a second protective layer over some of the plurality of protected material lines having the first critical dimension and some of the oxidized material lines having the second critical dimension, and oxidizing the unprotected material lines so that the oxidized unprotected material lines have an increased third critical dimension greater than the first critical dimension.

公开(公告)号：US09780185B2

公开(公告)日：2017-10-03

申请号：US15232300

申请日：2016-08-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hyun-Jin Cho ,  Tenko Yamashita ,  Hui Zang

IPC: H01L29/51 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/28 ,  H01L27/12

CPC classification number: H01L29/512 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.

公开(公告)号：US09601490B2

公开(公告)日：2017-03-21

申请号：US15040953

申请日：2016-02-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Hoon Kim

IPC: H01L27/092 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L21/28088 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795

Abstract: An improved method and structure for fabrication of replacement metal gate (RMG) field effect transistors is disclosed. P-type field effect transistor (PFET) gate cavities are protected while N work function metals are deposited in N-type field effect transistor (NFET) gate cavities.

公开(公告)号：US09570318B1

公开(公告)日：2017-02-14

申请号：US14805527

申请日：2015-07-22

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Jin Cho ,  MiaoMiao Wang ,  Hui Zang

IPC: H01L27/088 ,  H01L21/321 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/28

CPC classification number: H01L29/513 ,  H01L21/28026 ,  H01L21/324 ,  H01L29/41791 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Embodiments are directed to a method of forming portions of a fin-type field effect transistor (FinFET). The method includes forming at least one fin, and forming a dielectric layer over at least a portion of the at least one fin. The method further includes forming a work function layer over at least a portion of the dielectric layer. The method further includes forming a source region or a drain region adjacent the at least one fin, and performing an anneal operation, wherein the anneal operation anneals the dielectric layer and either the source region or the drain region, and wherein the work function layer provides a protection function to the at least a portion of the dielectric layer during the anneal operation.

Abstract translation: 实施例涉及一种形成鳍型场效应晶体管（FinFET）的部分的方法。 该方法包括形成至少一个翅片，并且在至少一个翅片的至少一部分上形成电介质层。 该方法还包括在电介质层的至少一部分上形成功函数层。 所述方法还包括形成与所述至少一个鳍片相邻的源极区域或漏极区域，以及执行退火操作，其中所述退火操作使所述电介质层和所述源极区域或所述漏极区域退火，并且其中所述功函数层提供 在退火操作期间到介电层的至少一部分的保护功能。

公开(公告)号：US20170033023A1

公开(公告)日：2017-02-02

申请号：US15292184

申请日：2016-10-13

Applicant: International Business Machines Corporation ,  Globalfoundries, Inc.

Inventor： Tenko Yamashita ,  Chun-Chen Yeh ,  Hui Zang

IPC: H01L21/66 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L22/32 ,  H01L21/76895 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L22/34 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/7851

Abstract: Embodiments are directed to a method Embodiments are directed to a test structure of a fin-type field effect transistor (FinFET). The test structure includes a first conducting layer electrically coupled to a dummy gate of the FinFET, and a second conducting layer electrically coupled to a substrate of the FinFET. The test structure further includes a third conducting layer electrically coupled to the dummy gate of the FinFET, and a first region of the FinFET at least partially bound by the first conducting layer and the second conducting layer. The test structure further includes a second region of the FinFET at least partially bound by the second conducting layer and the third conducting layer, wherein the first region comprises a first dielectric having a first dimension, and wherein the second region comprises a second dielectric having a second dimension greater than the first dimension.

公开(公告)号：US20160365348A1

公开(公告)日：2016-12-15

申请号：US15232246

申请日：2016-08-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hyun-Jin Cho ,  Tenko Yamashita ,  Hui Zang

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/512 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.

公开(公告)号：US20160365290A1

公开(公告)日：2016-12-15

申请号：US15232300

申请日：2016-08-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hyun-Jin Cho ,  Tenko Yamashita ,  Hui Zang

IPC: H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L29/512 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.