公开(公告)号：US20190214074A1

公开(公告)日：2019-07-11

申请号：US16215275

申请日：2018-12-10

Applicant: Rambus Inc.

Inventor： Craig E. HAMPEL ,  Richard E. PEREGO ,  Stefanos SIDIROPOULOS ,  Ely K. TSERN ,  Frederick A. WARE

IPC: G11C11/4076 ,  G11C11/4093 ,  G11C7/10 ,  G06F3/06 ,  G06F12/02 ,  G11C21/00 ,  G11C11/406 ,  H04L7/00 ,  G11C11/4072 ,  G11C11/4078 ,  G11C7/22

Abstract: A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

公开(公告)号：US20190196992A1

公开(公告)日：2019-06-27

申请号：US16228695

申请日：2018-12-20

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Ian P. Shaeffer ,  John Eble

IPC: G06F13/16 ,  G06F1/06 ,  G06F1/04 ,  G06F1/08 ,  G06F1/10 ,  G11C7/22

CPC classification number: G06F13/1689 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  G06F13/161 ,  G06F13/1657 ,  G11C7/04 ,  G11C7/222 ,  H04L7/033

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

公开(公告)号：US10332583B2

公开(公告)日：2019-06-25

申请号：US15898034

申请日：2018-02-15

Applicant: Rambus Inc.

Inventor： Jade M. Kizer ,  Sivakumar Doraiswamy ,  Benedict Lau

IPC: G11C7/00 ,  G11C11/4076 ,  G06F13/16 ,  G06F13/40 ,  G11C8/18 ,  G11C7/22 ,  G11C11/4063 ,  G11C11/4072 ,  G11C11/4096

Abstract: An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal.

公开(公告)号：US10331587B2

公开(公告)日：2019-06-25

申请号：US15498065

申请日：2017-04-26

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Thomas J. Giovannini

IPC: G06F12/00 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22

Abstract: Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the information specified that the memory device output the timing reference signal. The memory controller subsequently samples the data output from the memory device based on information provided by the timing reference signal output from the memory device.

公开(公告)号：US20190173697A1

公开(公告)日：2019-06-06

申请号：US16182724

申请日：2018-11-07

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Fariborz Assaderaghi ,  Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Qi Lin

IPC: H04L25/03

CPC classification number: H04L25/03343 ,  H04L25/03057 ,  H04L25/0307 ,  H04L25/03885 ,  H04L2025/03356 ,  H04L2025/03433 ,  H04L2025/03617

Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

公开(公告)号：US10310999B2

公开(公告)日：2019-06-04

申请号：US15702987

申请日：2017-09-13

Applicant: Rambus Inc.

Inventor： Jared LeVan Zerbe ,  Kevin S. Donnelly ,  Stefanos Sidiropoulos ,  Donald C. Stark ,  Mark A. Horowitz ,  Leung Yu ,  Roxanne Vu ,  Jun Kim ,  Bruno W. Garlepp ,  Tsyr-Chyang Ho ,  Benedict Chung-Kwong Lau

IPC: G06F13/364 ,  G06F13/42 ,  G06F1/10 ,  G06F13/16 ,  H04L7/00 ,  G11C7/10 ,  G06F12/02 ,  G06F3/06 ,  G06F13/40 ,  H04L7/033

Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

公开(公告)号：US20190164588A1

公开(公告)日：2019-05-30

申请号：US16097579

申请日：2017-05-03

Applicant: RAMBUS INC.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Brent Steven Haukness ,  Kenneth L. Wright ,  Thomas Vogelsang

IPC: G11C11/403 ,  G11C11/406 ,  G11C11/409 ,  G11C11/408

Abstract: A memory component includes a first memory bank. The first memory bank has a plurality of sub-arrays having sub-rows of memory elements. The memory component includes a write driver, coupled to the first memory bank, to perform a write operation of an entire sub-row of a sub-array. To perform the write operation, the write driver is to load a burst of write data to the memory bank. The memory bank may then activate a plurality of sense amplifiers associated with a plurality of memory elements of the entire sub-row to load the burst of write data to the plurality of sense amplifiers.

公开(公告)号：US10306169B2

公开(公告)日：2019-05-28

申请号：US15013927

申请日：2016-02-02

Applicant: Rambus Inc.

Inventor： Michael Guidash ,  Craig M. Smith ,  Jay Endsley

IPC: H04N5/378

Abstract: A pixel in an integrated-circuit image sensor is enabled to output, throughout a sampling interval, an analog signal having an amplitude dependent, at least in part, on photocharge integrated within a photosensitive element of the pixel. A plurality of samples of the analog signal are generated during an initial portion of the sampling interval that is shorter than a settling time for a maximum possible level of the analog signal.

公开(公告)号：US20190149136A1

公开(公告)日：2019-05-16

申请号：US16195069

申请日：2018-11-19

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Brian S. Leibowitz ,  Qi Lin

IPC: H03K3/013 ,  H04L25/06 ,  H04L25/49 ,  G11C7/02 ,  H03K5/153

CPC classification number: H03K3/013 ,  G11C7/02 ,  H03K5/153 ,  H04L25/03057 ,  H04L25/066 ,  H04L25/4902 ,  H04L25/4917

Abstract: A system for communicating information between circuits is described. A transmit circuit provides pulse-amplitude-modulation (PAM) signals via a communication channel to a receiver. A circuit in the receiver determines digital values from the received signals using a time-varying threshold voltage, which varies during the bit-time. This approach may compensate for inter-symbol interference (ISI) to increase the voltage and timing margins of the system.

公开(公告)号：US10270442B2

公开(公告)日：2019-04-23

申请号：US16051291

申请日：2018-07-31

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh ,  Ian P. Shaeffer

IPC: H03K17/16 ,  H03K19/00 ,  G06F3/06 ,  G11C16/06 ,  G11C11/417 ,  G11C16/32 ,  G11C11/413 ,  G11C11/4063 ,  G11C11/401 ,  G11C11/41 ,  G11C16/26 ,  G11C11/419 ,  H03K19/0175 ,  G11C11/4093 ,  G06F13/40

Abstract: A memory control component outputs a memory write command to a memory IC and also outputs write data to be received via data inputs of the memory IC. Prior to reception of the write data within the memory IC, the memory control component asserts a termination control signal that causes the memory IC to apply to the data inputs a first on-die termination impedance during reception of the write data followed by a second on-die termination impedance after the write data has been received. The memory control component deasserts the termination control signal to cause the memory IC to apply no termination impedance to the data inputs.