公开(公告)号：US09911627B1

公开(公告)日：2018-03-06

申请号：US13864244

申请日：2013-04-17

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

IPC: H01L21/00 ,  H01L21/48

CPC classification number: H01L21/4871 ,  H01L21/823487 ,  H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/3732 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/60 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/0248 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/098 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for processing a 3D semiconductor device, the method including: processing a first layer comprising first transistors, forming a first power distribution grid to provide power to the first transistors, processing a second layer overlying the first transistors and including second transistors, where the second layer includes a through layer via with diameter of less than 150 nm, forming a second power distribution grid overlaying the second transistors, where the first power distribution grid includes first power conductors and the second power distribution grid includes second power conductors, and where the second power conductors are substantially wider or thicker than the first power conductors, and where the device includes a plurality of vias to connect the second power distribution grid to the first power distribution grid.

公开(公告)号：US09853089B2

公开(公告)日：2017-12-26

申请号：US15224929

申请日：2016-08-01

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Zeev Wurman

IPC: H01L27/24 ,  G11C13/00 ,  G03F9/00 ,  H01L21/822 ,  H01L21/84 ,  H01L23/544 ,  H01L21/762 ,  H01L27/02 ,  H01L27/06 ,  H01L27/088 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L45/00 ,  H01L23/48

CPC classification number: H01L27/2436 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L23/481 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/00011 ,  H01L2224/80001

Abstract: A semiconductor device, including: a first memory cell including a first transistor; a second memory cell including a second transistor, where the second transistor overlays the first transistor and the second transistor self-aligned to the first transistor; and a plurality of junctionless transistors, where at least one of the junctionless transistors controls access to at least one of the memory cells.

公开(公告)号：US20170221761A1

公开(公告)日：2017-08-03

申请号：US15488514

申请日：2017-04-16

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Zeev Wurman

IPC: H01L21/77 ,  H01L27/10 ,  H01L27/02 ,  H01L23/00 ,  H01L23/31 ,  H01L29/66 ,  H01L23/40

CPC classification number: H01L21/77 ,  B82Y10/00 ,  G11C16/0408 ,  G11C16/0483 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/84 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/4012 ,  H01L23/5286 ,  H01L24/01 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/1052 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/1203 ,  H01L27/2436 ,  H01L27/249 ,  H01L28/00 ,  H01L29/1033 ,  H01L29/66257 ,  H01L29/6659 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/78696 ,  H01L29/7881 ,  H01L29/792 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L2221/6835 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81001 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/014 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and the third transistor is controlled by a third control line, where the second transistor is overlaying the first transistor and the second transistor is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and the third control line, and where the second transistor and the third transistor are self-aligned.

公开(公告)号：US20170200715A1

公开(公告)日：2017-07-13

申请号：US15470866

申请日：2017-03-27

Applicant: Monolithic 3D Inc.

Inventor： Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

IPC: H01L27/06 ,  H01L27/108 ,  H01L21/762

CPC classification number: H01L27/0688 ,  H01L21/76254 ,  H01L21/823475 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5225 ,  H01L23/585 ,  H01L25/0657 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/10802 ,  H01L27/10897 ,  H01L28/00 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An Integrated Circuit device, including: first transistors and second transistors, where the first transistors and the second transistors each include a single crystal channel, where at least one of the second transistors overlays at least one of the first transistors with less than 1 micron distance apart, and where at least one of the second transistors is a dopant segregated schottky barrier transistor.

公开(公告)号：US09406670B1

公开(公告)日：2016-08-02

申请号：US14514386

申请日：2014-10-15

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong ,  Deepak C. Sekar ,  Zeev Wurman

IPC: H01L27/02 ,  H01L27/06 ,  H01L27/088 ,  H01L23/522 ,  H01L23/532 ,  H01L23/367 ,  H01L23/528

CPC classification number: H01L27/0688 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/268 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823871 ,  H01L21/84 ,  H01L23/367 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/544 ,  H01L24/73 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/458 ,  H01L29/66272 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66848 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/78639 ,  H01L29/78642 ,  H01L29/78645 ,  H01L29/808 ,  H01L29/812 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2924/00012 ,  H01L2924/01015

Abstract: A semiconductor device, including: a first layer including first transistors, the first transistors are interconnected by at least one metal layer including copper or aluminum; a second layer including second transistors, the first layer is overlaid by the second layer, where the second layer includes a plurality of through layer vias having a diameter of less than 200 nm, where the second transistors include a source contact, the source contact including a silicide, and where the silicide has a sheet resistance of less than 15 ohm/sq.

Abstract translation: 一种半导体器件，包括：包括第一晶体管的第一层，所述第一晶体管通过包括铜或铝的至少一个金属层互连; 第二层包括第二晶体管，第一层由第二层覆盖，其中第二层包括直径小于200nm的多个通孔通孔，其中第二晶体管包括源极接触，源极接触包括 硅化物，其中硅化物的薄层电阻小于15欧姆/平方。

公开(公告)号：US20160141274A1

公开(公告)日：2016-05-19

申请号：US15008444

申请日：2016-01-28

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/743 ,  H01L21/76898 ,  H01L23/36 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5225 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/78 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01104 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/2064 ,  H01L2924/351 ,  H01L2924/00

Abstract: An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; a first wire structure constructed to provide power to a portion of the first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second single crystal transistors, the second layer overlying the at least one metal layer; and a second wire structure constructed to provide power to a portion of the second transistors, where the second wire structure is isolated from the first wire structure to provide a different power voltage to the portion of the second transistors.

Abstract translation: 一种集成电路器件，包括：包括单晶的基底晶片，所述基底晶片包括多个第一晶体管; 提供所述多个第一晶体管之间的互连的至少一个金属层; 构造成向所述第一晶体管的一部分提供功率的第一线结构; 第二层小于2微米厚，第二层包括多个第二单晶晶体管，第二层覆盖至少一个金属层; 以及第二线结构，其被构造成向所述第二晶体管的一部分提供电力，其中所述第二线结构与所述第一线结构隔离以向所述第二晶体管的所述部分提供不同的功率电压。

公开(公告)号：US09305867B1

公开(公告)日：2016-04-05

申请号：US14472108

申请日：2014-08-28

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/48 ,  H01L23/50 ,  H01L23/34 ,  H01L27/088

CPC classification number: H01L23/481 ,  H01L21/743 ,  H01L23/34 ,  H01L23/50 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0623 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/1066 ,  H01L29/66272 ,  H01L29/66704 ,  H01L29/66825 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/7841 ,  H01L29/808 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/16152 ,  H01L2924/00

Abstract: An Integrated Circuit device including: a first layer including first transistors; a first metal layer overlaying the first transistors and providing at least one connection to the first transistors; a second metal layer overlaying the first metal layer; and a second layer including second transistors overlaying the second metal layer, where the second metal layer is connected to provide power to at least one of the second transistors and a connection path between the second transistors and the second metal layer, where the connection path includes at least one through-layer via, and where the through-layer via has a diameter less than 150 nm.

Abstract translation: 一种集成电路装置，包括：包括第一晶体管的第一层; 覆盖所述第一晶体管并且提供至少一个到所述第一晶体管的连接的第一金属层; 覆盖所述第一金属层的第二金属层; 以及第二层，包括覆盖所述第二金属层的第二晶体管，其中所述第二金属层被连接以向所述第二晶体管中的至少一个提供功率，以及所述第二晶体管和所述第二金属层之间的连接路径，其中所述连接路径包括 至少一个贯通层通孔，并且其中贯通层通孔具有小于150nm的直径。

公开(公告)号：US09299641B2

公开(公告)日：2016-03-29

申请号：US14747599

申请日：2015-06-23

Applicant: Monolithic 3D Inc.

Inventor： Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

IPC: H01L23/48 ,  H01L27/088 ,  H01L23/367 ,  H01L23/522 ,  H01L27/06

CPC classification number: H01L25/0657 ,  H01L21/823475 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5225 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A 3D device including: a first layer including first transistors, the first layer overlaid by at least one interconnection layer; a second layer including second transistors, the second layer overlaying the interconnection layer; a plurality of electrical connections connecting the second transistors with the interconnection layer; and at least one thermally conductive and electrically non-conductive contact, where the at least one thermally conductive and electrically non-conductive contact thermally connects the second layer to a top or bottom surface of the 3D device.

Abstract translation: 一种3D设备，包括：包括第一晶体管的第一层，由至少一个互连层覆盖的第一层; 第二层，包括第二晶体管，第二层覆盖互连层; 将所述第二晶体管与所述互连层连接的多个电连接; 以及至少一个导热和非导电接触，其中所述至少一个导热和非导电接触将所述第二层热连接到所述3D器件的顶表面或底表面。

公开(公告)号：US20160035722A1

公开(公告)日：2016-02-04

申请号：US14880276

申请日：2015-10-11

Applicant: MONOLITHIC 3D INC.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L27/088 ,  H01L29/45

CPC classification number: H01L29/456 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/544 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66704 ,  H01L29/66772 ,  H01L29/78654 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An Integrated Circuit device, including: a first layer including first transistors; and a second layer including second transistors overlaying the first layer, where the first transistors are facing down and the second transistors are facing up, and where the second layer includes a through layer via of less than 300 nm diameter.

Abstract translation: 一种集成电路器件，包括：包括第一晶体管的第一层; 以及第二层，包括覆盖第一层的第二晶体管，其中第一晶体管面向下并且第二晶体管面向上，并且其中第二层包括直径小于300nm的贯穿层通孔。

公开(公告)号：US08836073B1

公开(公告)日：2014-09-16

申请号：US13959994

申请日：2013-08-06

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak Sekar ,  Brian Cronquist

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/48 ,  H01L27/06 ,  H01L23/544 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L23/481 ,  H01L21/743 ,  H01L23/34 ,  H01L23/50 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0623 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/1066 ,  H01L29/66272 ,  H01L29/66704 ,  H01L29/66825 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/7841 ,  H01L29/808 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/16152 ,  H01L2924/00

Abstract: An Integrated Circuit device including: a first layer of first transistors; a first metal layer overlaying the first transistors and providing at least one connection to the first transistors; a second metal layer overlaying the first metal layer; and a second layer of second transistors overlaying the second metal layer, where the second metal layer is connected to provide power to at least one of the second transistors.

Abstract translation: 一种集成电路装置，包括：第一层第一晶体管; 覆盖所述第一晶体管并且提供至少一个到所述第一晶体管的连接的第一金属层; 覆盖所述第一金属层的第二金属层; 以及覆盖所述第二金属层的第二层第二晶体管，其中所述第二金属层被连接以向所述第二晶体管中的至少一个提供功率。