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公开(公告)号：US09436610B2
公开(公告)日：2016-09-06
申请号：US14464750
申请日：2014-08-21
Applicant: STMicroelectronics International N.V.
Inventor： Gilles Ries , Ennio Salemi , Sana Ben Alaya
CPC classification number: G06F12/0862 , G06F12/1027 , G06F12/1063 , G06F2212/304 , G06F2212/507 , G06F2212/602 , G06F2212/684
Abstract: A memory management unit may send page table walk requests to a page table descriptor in a main memory system and receive address translation information, with the page table walk requests including information that specifies an amount of further address translation information, and receive the further address translation information. The cache unit may intercept the page table walk requests, and modify content of the intercepted page table walk requests so the information that specifies the amount of further address translation information is extended from a first amount to a second amount greater than the first amount. The cache unit may store the second amount of further address translation information for use with data requests that are subsequent to a current data request, and provide the address translation information based upon an intercepted page table walk request being associated with address translation information already stored in the cache unit.
Abstract translation: 存储器管理单元可以将页面表移动请求发送到主存储器系统中的页表描述符并且接收地址转换信息，其中页表步行请求包括指定进一步的地址转换信息的量的信息，并且接收另外的地址转换 信息。 高速缓存单元可以拦截页表行走请求，并且修改被拦截的页表行走请求的内容，使得指定进一步的地址转换信息量的信息从第一数量扩展到大于第一数量的第二数量。 高速缓存单元可以存储第二数量的进一步的地址转换信息，以便与当前数据请求之后的数据请求一起使用，并且基于与已经存储在地址转换信息中的地址转换信息相关联的被拦截的页表移动请求来提供地址转换信息 缓存单元。
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公开(公告)号：US09407224B2
公开(公告)日：2016-08-02
申请号：US14311086
申请日：2014-06-20
Applicant: STMicroelectronics International N.V.
Inventor： Carlo Pinna , Alessandro Mecchia , Paolo Pesenti
Abstract: The present disclosure refers to a digital microphone device providing a single-bit Pulse Density Modulation PDM output signal. The digital microphone comprises a microphone, arranged to convert an acoustic input signal into an analog electrical signal, and a preamplifier, having a variable gain, arranged to receive the analog electrical signal and to provide an amplified analog electrical signal, depending on the variable gain. The variable gain depends on a gain control signal. The digital microphone further comprises an Analog-to-Digital Converter block, arranged to receive the amplified analog electrical signal and to convert it into a respective digital signal; and a compensation block, arranged to receive the digital signal and to perform a digital operation on such digital signal, on the basis of a compensation signal, to generate a compensated signal. Furthermore, the digital microphone comprises an Automatic Gain Controller block 25, arranged to detect the digital signal and to generate said gain control signal, on the basis of the detected digital signal. The Automatic Gain Controller block is further arranged to generate the compensation signal, on the basis of the control signal, and to provide the compensation signal to the compensation block, to compensate a variation of the digital signal resulting from the variable gain of the preamplifier. Finally, the digital microphone device comprises a conversion block, arranged to receive the compensated signal and to convert it into the single-bit PDM output signal.
Abstract translation: 本公开涉及提供单位脉冲密度调制PDM输出信号的数字麦克风装置。 数字麦克风包括麦克风，其布置成将声输入信号转换为模拟电信号，以及具有可变增益的前置放大器，其布置成接收模拟电信号并根据可变增益提供放大的模拟电信号 。 可变增益取决于增益控制信号。 数字麦克风还包括模数转换器模块，被布置为接收放大的模拟电信号并将其转换成相应的数字信号; 以及补偿块，被布置成基于补偿信号接收数字信号并对这种数字信号执行数字操作，以产生补偿信号。 此外，数字麦克风包括自动增益控制器块25，其被布置为基于检测到的数字信号来检测数字信号并产生所述增益控制信号。 自动增益控制器块还被布置成基于控制信号产生补偿信号，并且向补偿块提供补偿信号，以补偿由前置放大器的可变增益引起的数字信号的变化。 最后，数字麦克风装置包括转换块，被布置成接收经补偿的信号并将其转换成单位PDM输出信号。
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公开(公告)号：US09379728B1
公开(公告)日：2016-06-28
申请号：US14751456
申请日：2015-06-26
Applicant: STMicroelectronics International N.V.
Inventor： Pratap Narayan Singh , Shiva Sharath Babu Kaleru , Ankur Bal , Mohit Singh , Rakesh Malik
CPC classification number: H03M1/1023 , H03M1/1047 , H03M1/66
Abstract: A digital-to-analog converter has an output. An analog-to-digital converter senses a voltage at the output of the digital-to-analog converter and generates a digital voltage signal. A source mismatch estimator processes the digital voltage signal to output an error signal indicative of current source mismatch within the digital-to-analog converter. An error code generator generates a digital calibration signal from the error signal. The digital calibration signal is converted by a redundancy digital-to-analog converter to an analog compensation signal for application to the output of analog-to-digital converter to nullify effects of the current source mismatch.
Abstract translation: 一个数模转换器有一个输出。 模拟 - 数字转换器感测数模转换器输出端的电压，并产生一个数字电压信号。 源不匹配估计器处理数字电压信号以输出指示数模转换器内的电流源失配的误差信号。 错误代码发生器从误差信号产生数字校准信号。 数字校准信号由冗余数模转换器转换为模拟补偿信号，以应用于模数转换器的输出，以消除电流源不匹配的影响。
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344.发明授权Oversampling CDR which compensates frequency difference without elasticity buffer 有权过采样CDR，补偿频率差，无弹性缓冲公开(公告)号：US09356770B2
公开(公告)日：2016-05-31
申请号：US14231499
申请日：2014-03-31
Applicant: STMicroelectronics International N.V.
Inventor： Abhishek Chowdhary , Vivek Uppal , Alok Kaushik , Sajal Kumar Mandal , Tapas Nandy , Sanjeev Chopra
CPC classification number: H04L7/0087 , H03L7/0807 , H03L7/091 , H04L7/0004 , H04L7/005 , H04L7/033 , H04L7/0331 , H04L7/0338 , H04L25/03057 , H04L43/022
Abstract: A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter.
Abstract translation: 补偿过采样CDR中的频率差的方法，算法，架构，电路和/或系统。 过采样的CDR使用可编程分频器，其分频比从其通常的分频比改变一个或多个周期，当任一方向上的累积相位移动超过阈值时。 因此，过采样CDR中的弹性缓冲器可以被制造得更小或完全消除，导致较少的面积，并且减少或消除了最大允许突发尺寸对ppm差的依赖性。 门限可以保持可编程，并且超过一半单位间隔，以提供对高频抖动的鲁棒性。
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公开(公告)号：US20160149491A1
公开(公告)日：2016-05-26
申请号：US14549458
申请日：2014-11-20
Applicant: STMicroelectronics International N.V.
Inventor： Phalguni Bala , Hiten Advani
IPC: H02M3/158
CPC classification number: H02M3/06 , H02M2001/0022
Abstract: According to an embodiment, a circuit includes a protection voltage generator coupled to a first voltage node, a second voltage node, and a ground voltage node, the protection voltage generator configured to generate a plurality of protection voltages at a first plurality of nodes based on the first voltage node and the second voltage node, and a voltage protection ladder coupled between the first voltage node and a low voltage circuit, the voltage protection ladder coupled to the plurality of protection voltages at the first plurality of nodes, the voltage protection ladder configured to generate a first low voltage based on the first voltage node and the plurality of protection voltages.
Abstract translation: 根据实施例，电路包括耦合到第一电压节点，第二电压节点和接地电压节点的保护电压发生器，所述保护电压发生器被配置为在基于第一多个节点的基础上产生多个保护电压 所述第一电压节点和所述第二电压节点以及耦合在所述第一电压节点和低电压电路之间的电压保护梯，所述电压保护梯级耦合到所述第一多个节点处的所述多个保护电压，所述电压保护梯配置 以产生基于第一电压节点和多个保护电压的第一低电压。
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Patent Agency Ranking
346.发明授权公开(公告)号：US09342085B2
公开(公告)日：2016-05-17
申请号：US14512564
申请日：2014-10-13
Applicant: STMicroelectronics International N.V.
Inventor： Hemant Shukla , Saurabh Kumar Singh , Nitin Bansal
Abstract: An electronic device includes a power supply, a ground, and an intermediate ground having a voltage less than a voltage of the power supply and greater than a voltage of the ground. The electronic device also includes an error amplifier having an input stage coupled between the power supply and the ground, and an output stage coupled between the power supply and the intermediate ground. A ballast transistor is coupled to receive an output from the error amplifier. A feedback circuit is coupled to an output of the ballast transistor to generate feedback signals, and the error amplifier operates in response to the feedback signals.
Abstract translation: 电子设备包括电源，接地和具有小于电源电压的电压并且大于地的电压的中间接地。 电子设备还包括误差放大器，其具有耦合在电源和地之间的输入级，以及耦合在电源和中间接地之间的输出级。 耦合镇流器晶体管以接收来自误差放大器的输出。 反馈电路耦合到镇流器晶体管的输出以产生反馈信号，误差放大器响应于反馈信号而工作。
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347.发明申请公开(公告)号：US20160124445A1
公开(公告)日：2016-05-05
申请号：US14530448
申请日：2014-10-31
Applicant: STMicroelectronics International N.V.
Inventor： Rajeev Jain , Chandrajit Debnath
IPC: G05F1/46
Abstract: A bandgap voltage generator includes a plurality of calibration transistors. A test circuit measures the bandgap reference voltage generated by the bandgap voltage generator and enables a subset of the calibration transistors to correct to the bandgap reference voltage.
Abstract translation: 带隙电压发生器包括多个校准晶体管。 测试电路测量由带隙电压发生器产生的带隙参考电压，并使得校准晶体管的子集能够校正到带隙参考电压。
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348.发明授权Automatic power switching and power harvesting in thin oxide open drain transmitter circuits, systems, and methods 有权薄氧化物开漏发射器电路，系统和方法中的自动功率开关和功率采集公开(公告)号：US09331671B2
公开(公告)日：2016-05-03
申请号：US14283043
申请日：2014-05-20
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Nitin Gupta , Paramjeet Singh Sahni , Tapas Nandy , Manish Garg
CPC classification number: H03K3/01 , H03K19/018528 , H04N5/44 , H04N5/63
Abstract: A power harvesting circuit includes a new transmitter topology that ensures that no junction of thin oxide transistors forming the power harvesting circuit will experience a voltage across junctions of the transistors that is more than a maximum tolerable junction voltage. A supplemental power feed circuit operates to provide a supplemental feed current to components in a transmitter circuit when power harvested from a receiver circuit is insufficient to adequately power these components of the transmitter circuit, which may occur during high frequency operation of communications channels coupling the transmitter and receiver circuits. The supplemental power feed circuit also operates to sink a shunt current when power harvested from the receiver circuit is more than is needed to power the components in the transmitter circuit.
Abstract translation: 功率收集电路包括新的发射机拓扑结构，其确保形成功率收集电路的薄氧化物晶体管的结不会经受超过最大可容忍结电压的晶体管结的电压。 补充供电电路用于在从接收器电路收集的功率不足以对发射机电路的这些组件充分供电时，向发射机电路中的组件提供补充馈电电流，这可能在耦合发射机的通信信道的高频操作期间发生 和接收器电路。 当从接收器电路收集的功率大于为发射机电路中的组件供电所需的功率时，辅助馈电电路还用于吸收分流电流。
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349.发明授权Phase locked loop (PLL) circuit with compensated bandwidth across process, voltage and temperature 有权锁相环（PLL）电路，具有过程，电压和温度的补偿带宽公开(公告)号：US09325324B1
公开(公告)日：2016-04-26
申请号：US14573002
申请日：2014-12-17
Applicant: STMicroelectronics International N.V.
Inventor： Nitin Gupta , Anand Kumar , Abhirup Lahiri
CPC classification number: H03L7/099 , H03L1/00 , H03L7/0895 , H03L7/0898 , H03L7/0995 , H03L7/1072 , H03L7/113 , H03L7/18
Abstract: A phase locked loop (PLL) circuit includes a phase comparison circuit configured to compare phase of an input signal to phase of a feedback signal and generate a control signal responsive to the phase comparison and an oscillator circuit configured to generate an output signal at a frequency set by said control signal, where said feedback signal is derived from said output signal. The PLL circuit further operates in a calibration mode of operation wherein the oscillator circuit operates in a frequency locked loop mode to compare frequency of the input signal to frequency of the output signal and center a gain of the oscillator circuit across process, voltage and temperature in response to the frequency comparison. Furthermore, bias current for a charge pump within the phase comparison circuit is calibrated during calibration mode of operation to match a temperature independent reference current.
Abstract translation: 锁相环（PLL）电路包括相位比较电路，其被配置为将输入信号的相位与反馈信号的相位进行比较，并响应于相位比较产生控制信号，以及振荡器电路，被配置为产生频率的输出信号 由所述控制信号设置，其中所述反馈信号从所述输出信号导出。 PLL电路进一步在校准操作模式下工作，其中振荡器电路以频率锁定环路模式操作，以将输入信号的频率与输出信号的频率进行比较，并将振荡器电路的增益集中在过程，电压和温度之间 响应频率比较。 此外，相位比较电路内的电荷泵的偏置电流在校准操作模式下进行校准，以匹配与温度无关的参考电流。
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350.发明授权CMOS oscillator having stable frequency with process, temperature, and voltage variation 有权具有稳定频率的CMOS振荡器，具有过程，温度和电压变化公开(公告)号：US09325323B2
公开(公告)日：2016-04-26
申请号：US14474091
申请日：2014-08-30
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Vikas Rana , Ganesh Raj R
CPC classification number: H03L1/00 , H03K3/011 , H03K3/0315 , H03K3/0322 , H03K3/354 , H03L1/022 , H03L7/0812 , H03L7/0891 , H03L7/0895 , H03L7/093 , H03L7/0995 , H03L7/0997 , H03L7/148 , H03L7/18
Abstract: A clock signal generation circuit configured to generate the clock signal having a frequency that is maintained across variations in a number of operating conditions, such as changes in supply voltage, temperature and processing time. In an embodiment, the frequency spread of the generated clock signal of a PVT-compensated CMOS ring oscillator is configured to compensate for variations in the supply voltage, as well as for variations in process and temperature via a process and temperature compensation circuit. The PVT-compensated CMOS ring oscillator includes a regulated voltage supply circuit to generate a supply voltage that is resistant to variations due to changes in the overall supply voltage.
Abstract translation: 时钟信号生成电路，被配置为生成具有在诸如电源电压，温度和处理时间的变化的操作条件的数量的变化中保持的频率的时钟信号。 在一个实施例中，PVT补偿的CMOS环形振荡器的所产生的时钟信号的频率扩展被配置为补偿电源电压的变化，以及通过处理和温度补偿电路对工艺和温度的变化。 PVT补偿的CMOS环形振荡器包括一个稳压电源，用于产生一个电源电压，该电源电压抵抗由于整个电源电压的变化引起的变化。
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