公开(公告)号：US09847365B2

公开(公告)日：2017-12-19

申请号：US14960018

申请日：2015-12-04

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Nicolas Hotellier

IPC: H01L27/146 ,  H01L31/18 ,  H01L21/768

CPC classification number: H01L27/14636 ,  H01L21/76898 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14687 ,  H01L27/14689 ,  H01L31/1892 ,  H01L2224/05

Abstract: An electronic component includes a semiconductor layer having a first surface coated with a first insulating layer and a second surface coated with an interconnection structure. A laterally insulated conductive pin extends through the semiconductor layer from a portion of conductive layer of the interconnection structure all the way to a contact pad arranged at the level of the first insulating layer.

公开(公告)号：US09825080B2

公开(公告)日：2017-11-21

申请号：US14973344

申请日：2015-12-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Nayera Ahmed ,  François Roy

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14643 ,  H01L27/14685 ,  H01L27/14689 ,  H01L27/14698

Abstract: A structure of insulation between photodiodes formed in a doped semiconductor layer of a first conductivity type extending on a doped semiconductor substrate of the second conductivity type, the insulating structure including a trench crossing the semiconductor layer, the trench walls being coated with an insulating layer, the trench being filled with a conductive material and being surrounded with a P-doped area, more heavily doped than the semiconductor layer.

公开(公告)号：US20170299809A1

公开(公告)日：2017-10-19

申请号：US15132408

申请日：2016-04-19

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Frédéric BOEUF ,  Charles BAUDOT

IPC: G02B6/12 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48

CPC classification number: G02B6/12004 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/13 ,  H01L24/14 ,  H01L2924/00014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2224/13099

Abstract: An electro-optic device may include a substrate layer, and a first photonic layer over the substrate layer and having a first photonic device. The electro-optic device may include a second photonic layer over the first photonic layer and having a second photonic device. The electro-optic device may include a dielectric layer over the second photonic layer, and a first electrically conductive via extending through the dielectric layer and the second photonic layer to couple to the first photonic device, and a second electrically conductive via extending through the dielectric layer and coupling to the second photonic device. The electro-optic device may include a third electrically conductive via extending through the substrate layer, the second photonic layer, and the first photonic layer to couple to the substrate layer.

公开(公告)号：US20170271325A1

公开(公告)日：2017-09-21

申请号：US15454788

申请日：2017-03-09

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Olivier Weber ,  Emmanuel Richard ,  Philippe Boivin

IPC: H01L27/06 ,  H01L27/24 ,  H01L29/732 ,  H01L21/84 ,  H01L21/8249 ,  H01L45/00

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/1207 ,  H01L27/2445 ,  H01L29/0813 ,  H01L29/41708 ,  H01L29/66303 ,  H01L29/732 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/16

Abstract: Bipolar transistors and MOS transistors are formed in a common process. A semiconductor layer is arranged on an insulating layer. On a side of the bipolar transistors: an insulating region including the insulating layer is formed; openings are etched through the insulating region to delimit insulating walls; the openings are filled with first epitaxial portions; and the first epitaxial portions and a first region extending under the first epitaxial portions and under the insulating walls are doped. On the side of the bipolar transistors and on a side of the MOS transistors: gate structures are formed; second epitaxial portions are made; and the second epitaxial portions covering the first epitaxial portions are doped.

公开(公告)号：US09755610B2

公开(公告)日：2017-09-05

申请号：US14981189

申请日：2015-12-28

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Frederic Gianesello ,  Romain Pilard ,  Cedric Durand

IPC: H01F27/28 ,  H01F5/00 ,  H01F21/02 ,  H01F21/12 ,  H01F7/06 ,  H04B1/40 ,  H03H7/42 ,  H01F27/38 ,  H01L23/522 ,  H01F27/29 ,  H01F27/40 ,  H04W88/02

CPC classification number: H03H7/42 ,  H01F27/2804 ,  H01F27/29 ,  H01F27/38 ,  H01F27/40 ,  H01L23/5223 ,  H01L23/5227 ,  H01L2924/0002 ,  H04W88/02 ,  Y10T29/4902 ,  H01L2924/00

Abstract: A transformer of the balanced-unbalanced type includes a primary inductive circuit and a secondary inductive circuit housed inside an additional inductive winding connected in parallel to the terminals of the secondary circuit and inductively coupled with the primary circuit and the secondary circuit.

公开(公告)号：US09735772B2

公开(公告)日：2017-08-15

申请号：US14865618

申请日：2015-09-25

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Alexandre Dray ,  Emmanuel Josse

IPC: H01L25/00 ,  H03K17/687 ,  H01L21/66 ,  G01R31/28 ,  H01L27/02

CPC classification number: H03K17/687 ,  G01R31/2884 ,  H01L22/22 ,  H01L22/34 ,  H01L27/0207

Abstract: An integrated circuit includes at least one integrated cell disposed at a location of the integrated circuit. The at least one integrated cell may have two integrated devices coupled to at least one site of the integrated cell and a multiplexer, and the two integrated devices respectively oriented in two different directions of orientation. A first integrated device of the two integrated devices that is oriented in one of the two directions of orientation is usable. The integrated circuit may include a controller configured to detect the direction of orientation which, having regard to the disposition of the integrated cell at the location, may allow the first integrated device to be usable, and to control the multiplexer to couple the first integrated device electrically to the at least one site.

公开(公告)号：US20170221946A1

公开(公告)日：2017-08-03

申请号：US15488691

申请日：2017-04-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy ,  Philippe Are

IPC: H01L27/146 ,  H01L27/148

CPC classification number: H01L27/14607 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/14614 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/14638 ,  H01L27/14643 ,  H01L27/14812

Abstract: An image sensor includes a control circuit and pixels. Each pixel includes: a photosensitive area, a substantially rectangular storage area adjacent to the photosensitive area, and a read area. First and second insulated vertical electrodes electrically connected to each other are positioned opposite each other and delimit the storage area. The first electrode extends between the storage area and the photosensitive area. The second electrode includes a bent extension opposite a first end of the first electrode, with the storage area emerging onto the photosensitive area on the side of the first end. The control circuit operates to apply a first voltage to the first and second electrodes to perform a charge transfer, and a second voltage to block charge transfer.

公开(公告)号：US09722166B2

公开(公告)日：2017-08-01

申请号：US13741201

申请日：2013-01-14

Applicant: STMicroelectronics (Crolles 2) SAS ,  Centre National de la Recherche Scientifique

Inventor： Stéphane Monfray ,  Thomas Skotnicki ,  Emmanuel Dubois

IPC: H02N1/00 ,  H01L35/32 ,  H01L37/00 ,  H01J45/00

CPC classification number: H01L35/32 ,  H01J45/00 ,  H01L37/00

Abstract: A tunnel-effect power converter including first and second electrodes having opposite surfaces, wherein the first electrode includes protrusions extending towards the second electrode.

公开(公告)号：US20170194350A1

公开(公告)日：2017-07-06

申请号：US15137540

申请日：2016-04-25

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean Jimenez

IPC: H01L27/12 ,  H01L29/10 ,  H01L29/417 ,  H01L29/06

CPC classification number: H01L27/1203 ,  H01L21/76283 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/41733 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78696

Abstract: An integrated circuit includes a MOS transistor situated in and on an active region of a semiconductor substrate. The active region is bounded by an insulating region for example of the shallow trench isolation type. The drain region of the transistor is positioned in the semiconductor substrate situated away from the insulating region. An insulated gate of the transistor includes a central opening that is positioned in alignment with the drain region. A channel region of the transistor is annularly surrounds the drain region.

公开(公告)号：US20170192170A1

公开(公告)日：2017-07-06

申请号：US14984563

申请日：2015-12-30

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Charles BAUDOT ,  Alain CHANTRE ,  Sébastien CREMER

IPC: G02B6/122 ,  G02B6/42 ,  G02B6/34 ,  G02B6/136 ,  G02B6/132

CPC classification number: G02B6/122 ,  G02B6/132 ,  G02B6/136 ,  G02B6/34 ,  G02B6/4201 ,  G02B6/4214 ,  G02B2006/12147

Abstract: A method is for making a photonic chip including EO devices having multiple thicknesses. The method may include forming a first semiconductor layer over a semiconductor film, forming a second semiconductor layer over the first semiconductor layer, and forming a mask layer over the second semiconductor layer. The method may include performing a first selective etching of the mask layer to provide initial alignment trenches, performing a second etching, aligned with some of the initial alignment trenches and using the first semiconductor layer as an etch stop, to provide multi-level trenches, and filling the multi-level trenches to make the EO devices having multiple thicknesses.