公开(公告)号：US20130010826A1

公开(公告)日：2013-01-10

申请号：US13176599

申请日：2011-07-05

Applicant: Olivier Le Neel ,  Suman Cherian ,  Ravi Shankar

Inventor： Olivier Le Neel ,  Suman Cherian ,  Ravi Shankar

IPC: G01K13/00 ,  H01L21/02

CPC classification number: G01N27/3272 ,  G01N33/49

Abstract: Microsensors that include an integrated thermal energy source and an integrated temperature sensor are capable of providing localized heating and temperature control of individual sensing regions within the microsensor. Localized temperature control allows analyte detection to be carried out at the same temperatures or substantially the same temperatures at which the sensor is calibrated. By carrying out the sensing near the calibration temperature, more accurate results can be obtained. In addition, the temperature of the sensing region can be controlled so that chemical reactions involving the analyte in the sensing region occur near their peak reaction rate. Carrying out the sensing near the peak reaction rate improves the sensitivity of the sensor which is important as sensor dimensions decrease and the magnitude of the generated signals decreases.

Abstract translation: 包括集成热能源和集成温度传感器的微型传感器能够提供微传感器内各个感测区域的局部加热和温度控制。 局部温度控制允许分析物检测在相同的温度或基本相同的温度下进行，在此温度下传感器被校准。 通过在校准温度附近进行感测，可以获得更准确的结果。 此外，可以控制感测区域的温度，使得涉及感测区域中的分析物的化学反应在峰值反应速率附近发生。 在峰值反应速率附近进行感测提高了传感器的灵敏度，这在传感器尺寸减小并且产生的信号的幅度减小时是重要的。

公开(公告)号：US20120171875A1

公开(公告)日：2012-07-05

申请号：US12982707

申请日：2010-12-30

Applicant: Kah Wee Gan ,  Yonggang Jin

Inventor： Kah Wee Gan ,  Yonggang Jin

IPC: H01L21/324 ,  F27D3/00

CPC classification number: H01L21/67288

Abstract: A system and method for reducing warpage of a semiconductor wafer. The system includes a device for securing the semiconductor wafer in a heating area. The device includes a holding mechanism for securing an edge of the semiconductor wafer. The device further includes a pressure reducing device that reduces the pressure underneath the semiconductor device, which further secures the semiconductor device in the heating area. The heating area includes a plurality of heating and cooling zones in which the semiconductor wafer is subjected to various temperatures.

Abstract translation: 一种减少半导体晶片翘曲的系统和方法。 该系统包括用于将半导体晶片固定在加热区域中的装置。 该装置包括用于固定半导体晶片的边缘的保持机构。 该装置还包括减压装置，其降低半导体器件下方的压力，这进一步将半导体器件固定在加热区域中。 加热区域包括多个加热和冷却区域，其中半导体晶片经受各种温度。

公开(公告)号：US20120168943A1

公开(公告)日：2012-07-05

申请号：US12982719

申请日：2010-12-30

Applicant: Kah Wee Gan ,  Yonggang Jin ,  Anandan Ramasamy ,  Yun Liu

Inventor： Kah Wee Gan ,  Yonggang Jin ,  Anandan Ramasamy ,  Yun Liu

IPC: H01L23/485 ,  H01L21/50

CPC classification number: H01L24/96 ,  H01L21/561 ,  H01L21/568 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/08235 ,  H01L2224/12105 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014

Abstract: A semiconductor package and method of forming the same is described. The semiconductor package is formed from a semiconductor die cut from a semiconductor wafer that has a passivation layer. The semiconductor wafer is exposed to ionized gas causing the passivation layer to roughen. The semiconductor wafer is cut to form a plurality of semiconductor dies each with a roughened passivation layer. The plurality of semiconductor dies are placed on an adhesive layer to form a reconstituted wafer, and an encapsulation layer is formed enclosing the adhesive layer and the plurality of semiconductor dies. The passivation layer is removed and the semiconductor package formed includes electrical contacts for establishing electrical connections external to the semiconductor package.

Abstract translation: 描述了半导体封装及其形成方法。 半导体封装由从具有钝化层的半导体晶片切割的半导体管芯形成。 将半导体晶片暴露于电离气体，导致钝化层变粗糙。 切割半导体晶片以形成多个具有粗糙化钝化层的半导体管芯。 多个半导体管芯被放置在粘合剂层上以形成重构的晶片，并且形成包封粘合剂层和多个半导体管芯的封装层。 去除钝化层，形成的半导体封装包括用于在半导体封装外部建立电连接的电触头。

公开(公告)号：US20120168929A1

公开(公告)日：2012-07-05

申请号：US12982722

申请日：2010-12-30

Applicant: Kim-Yong Goh

Inventor： Kim-Yong Goh

IPC: H01L23/34 ,  H01L21/60 ,  H01L21/56

CPC classification number: H01L23/13 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/1184 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92163 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/30107 ,  H01L2224/85 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package is formed having a substrate juxtaposed on at least two sides of a semiconductor die. Both the substrate and the semiconductor die are affixed to a conductive layer that draws heat generated during use of the semiconductor package away from the semiconductor die and the substrate. There are also electrical contacts affixed to the substrate and the semiconductor die. The electrical contacts facilitate electrical connection between the semiconductor die, the substrate, and any external devices or components making use of the semiconductor die. The substrate, semiconductor die, and at least a portion of some of the electrical contacts are enclosed by an encapsulating layer insulating the components. Portions of the electrical contacts not enclosed by the encapsulating layer are affixed to an outside device, such as a printed circuit board.

Abstract translation: 形成半导体封装，其具有并置在半导体管芯的至少两侧上的衬底。 衬底和半导体管芯都固定到导电层，该导电层将半导体封装的使用期间产生的热量从半导体管芯和衬底上吸取。 还存在固定到基板和半导体管芯上的电触点。 电触点促进半导体管芯，衬底和利用半导体管芯的任何外部器件或器件之间的电连接。 衬底，半导体管芯和一些电触点的至少一部分被封装在绝缘元件的封装层上。 没有被封装层包围的电触点的部分固定在诸如印刷电路板的外部装置上。

公开(公告)号：US20120161319A1

公开(公告)日：2012-06-28

申请号：US12978144

申请日：2010-12-23

Applicant: Yaohuang Huang ,  Yonggang Jin ,  Puay Gek Chua ,  How Yuan Hwang

Inventor： Yaohuang Huang ,  Yonggang Jin ,  Puay Gek Chua ,  How Yuan Hwang

IPC: H01L21/02 ,  H01L23/482

CPC classification number: H01L24/03 ,  H01L23/53238 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02166 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/0239 ,  H01L2224/034 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03616 ,  H01L2224/0381 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/11334 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/01074 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A process for making an integrated circuit, a wafer level integrated circuit package or an embedded wafer level package includes forming copper contact pads on a substrate or substructure. The substructure may include devices and the contact pads may be used for forming electrical couplings to the devices. For example, copper plating may be applied to a substructure and the copper plating etched to form copper contact pads on the substructure. An etching process may be applied to remove barrier layer material on the substructure, such as adjacent to the copper pads. For example, a hydrogen peroxide etch may be applied to remove titanium-tungsten from a surface of the substructure. The pads are again etched to remove barrier layer etchant, byproducts and/or oxide from the pads. Contamination control steps may be performed, such as quick-dump-and-rinse (QDR) and spin-rinse-and-dry (SRD) processing.

Abstract translation: 制造集成电路，晶片级集成电​​路封装或嵌入晶片级封装的工艺包括在衬底或子结构上形成铜接触焊盘。 子结构可以包括装置，并且接触垫可以用于形成到装置的电耦合。 例如，可以将铜电镀施加到子结构上，并且蚀刻铜电镀以在子结构上形成铜接触焊盘。 可以应用蚀刻工艺以去除子结构上的阻挡层材料，例如邻近铜焊盘。 例如，可以施加过氧化氢蚀刻以从底层结构的表面去除钛 - 钨。 再次蚀刻焊盘以从焊盘去除阻挡层蚀刻剂，副产物和/或氧化物。 可以执行污染控制步骤，例如快速冲洗和冲洗（QDR）和旋转冲洗干燥（SRD）处理。

公开(公告)号：US20120139076A1

公开(公告)日：2012-06-07

申请号：US12961311

申请日：2010-12-06

Applicant: Ravi Shankar ,  Olivier Le Neel

Inventor： Ravi Shankar ,  Olivier Le Neel

IPC: H01L23/36 ,  H01L21/02

CPC classification number: H01L23/38 ,  H01L27/0814 ,  H01L27/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor thermoelectric cooler includes P-type and N-type thermoelectric cooling elements. The P-type and N-type thermoelectric elements have a first portion having a first cross-sectional area and a second portion having a second cross-sectional area larger than the first cross-sectional area. The P-type and N-type thermoelectric cooling elements may, for example, be T-shaped or L-shaped. In another example, the thermoelectric cooling elements have a first surface having a first shape configured to couple to a first electrical conductor and a second surface opposite the first surface and having a second shape, different from the first shape, and configured to couple to a second electrical conductor. For example, the first surface may have a rectilinear shape of a first area and the second surface may have a rectilinear shape of a second area different from the first area. The semiconductor thermoelectric cooler may be manufactured using thin film technology.

Abstract translation: 半导体热电冷却器包括P型和N型热电冷却元件。 P型和N型热电元件具有具有第一横截面积的第一部分和具有大于第一横截面积的第二横截面积的第二部分。 P型和N型热电冷却元件例如可以是T形或L形。 在另一个示例中，热电冷却元件具有第一表面，该第一表面具有被配置为耦合到第一电导体和与第一表面相对的第二表面并且具有与第一形状不同的第二形状的第一形状，并且被配置为耦合到 第二电导体。 例如，第一表面可以具有第一区域的直线形状，并且第二表面可以具有与第一区域不同的第二区域的直线形状。 半导体热电冷却器可以使用薄膜技术制造。

公开(公告)号：US20120139075A1

公开(公告)日：2012-06-07

申请号：US12961229

申请日：2010-12-06

Applicant: Ravi Shankar ,  Olivier Le Neel

Inventor： Ravi Shankar ,  Olivier Le Neel

IPC: H01L23/34 ,  H01L21/329

CPC classification number: H01L23/38 ,  H01L27/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor thermoelectric cooler is configured to direct heat through channels of the cooler. The thermoelectric cooler has multiple electrodes and a first dielectric material positioned between side surfaces of the electrodes. A second dielectric material, different from the first dielectric material, is in contact with top surfaces of the electrodes. The first dielectric material extends above the top surface of the electrodes, separating portions of the second dielectric material, and is in contact with a portion of the top surfaces of the electrodes. The first dielectric material has a thermal conductivity different than a thermal conductivity of the second dielectric material. A ratio of the first dielectric material to the second dielectric material in contact with the top surface of the electrodes may be selected to control the heat retention. The semiconductor thermoelectric cooler may be manufactured using thin film technology.

Abstract translation: 半导体热电冷却器构造成通过冷却器的通道引导热量。 热电冷却器具有多个电极和位于电极的侧表面之间的第一介电材料。 与第一介电材料不同的第二介电材料与电极的顶表面接触。 第一电介质材料在电极的顶表面上方延伸，分离第二介电材料的部分，并与电极的顶表面的一部分接触。 第一电介质材料具有不同于第二电介质材料的热导率的导热系数。 可以选择与电极的顶表面接触的第一电介质材料与第二电介质材料的比例以控制保温。 半导体热电冷却器可以使用薄膜技术制造。

公开(公告)号：US20120112873A1

公开(公告)日：2012-05-10

申请号：US13340255

申请日：2011-12-29

Applicant: Olivier Le Neel ,  Stefania Maria Serena Privitera ,  Pascale Dumont-Girard ,  Maurizio Gabriele Castorina ,  Calvin Leung

Inventor： Olivier Le Neel ,  Stefania Maria Serena Privitera ,  Pascale Dumont-Girard ,  Maurizio Gabriele Castorina ,  Calvin Leung

IPC: H01C1/08 ,  H01C17/06 ,  H01C17/00

CPC classification number: H01C17/265 ,  H01C17/0656 ,  H01L23/345 ,  H01L23/5228 ,  H01L24/05 ,  H01L27/016 ,  H01L27/0688 ,  H01L28/20 ,  H01L2224/02166 ,  H01L2924/01019 ,  H01L2924/1301 ,  H01L2924/13033 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

Abstract: A process is described for integrating two closely spaced thin films without deposition of the films through deep vias. The films may be integrated on a wafer and patterned to form a microscale heat-trimmable resistor. A thin-film heating element may be formed proximal to a thin-film resistive element, and heat generated by the thin-film heater can be used to permanently trim a resistance value of the thin-film resistive element. Deposition of the thin films over steep or abrupt topography is minimized by using a process in which the thin films are deposited in a sequence that falls between depositions of thick metal contacts to the thin films.

Abstract translation: 描述了一种用于集成两个紧密间隔的薄膜而不通过深通孔沉积膜的方法。 膜可以集成在晶片上并被图案化以形成微量热可调节电阻器。 可以在薄膜电阻元件的近侧形成薄膜加热元件，并且可以使用由薄膜加热器产生的热量来永久地修整薄膜电阻元件的电阻值。 通过使用其中薄膜以厚的金属接触沉积到薄膜之间的顺序沉积的方法，使得在陡峭或突然形貌上的薄膜沉积最小化。

公开(公告)号：US20120038043A1

公开(公告)日：2012-02-16

申请号：US13280186

申请日：2011-10-24

Applicant: Yonggang Jin

Inventor： Yonggang Jin

IPC: H01L23/485

CPC classification number: H01L23/5389 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/19 ,  H01L24/24 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

Abstract: Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface and a bond pad defined on the top surface, and a substrate having a cavity. An adhesive layer is positioned between a top surface of the cavity and the bottom surface of the integrated circuit, and a bump is positioned proximate a top surface of the fan-out wafer level packaging, the bump spaced apart from the integrated circuit. A redistribution layer is configured to electrically couple the bond pad of the integrated circuit to the bump.

Abstract translation: 扇出晶片级封装包括具有顶表面，底表面和限定在顶表面上的接合焊盘的集成电路和具有空腔的基板。 粘合剂层位于空腔的顶表面和集成电路的底表面之间，并且凸起位于扇形晶片级封装的顶表面附近，凸起与集成电路间隔开。 再分配层被配置为将集成电路的接合焊盘电连接到凸块。