公开(公告)号：US07186662B2

公开(公告)日：2007-03-06

申请号：US10964841

申请日：2004-10-13

Applicant: Chien-Hao Chen ,  Chia-Jen Chen ,  Tze-Liang Lee ,  Chao-Cheng Chen ,  Shih-Chang Chen

Inventor： Chien-Hao Chen ,  Chia-Jen Chen ,  Tze-Liang Lee ,  Chao-Cheng Chen ,  Shih-Chang Chen

IPC: H01L21/461

CPC classification number: H01L21/28123 ,  H01L21/0217 ,  H01L21/28035 ,  H01L21/31608 ,  H01L21/3185

Abstract: A method for forming a hard mask for gate electrode patterning in a semiconductor device is disclosed. The method includes providing a polysilicon layer to be etched and forming over the polysilicon layer, a nitride hardmask with a relatively high etch rate to hydrofluoric acid, as compared to the etch rate of silicon oxide. The polysilicon can then be patterned using the hardmask and the hardmask can be removed using hydrofluoric acid.

Abstract translation: 公开了一种在半导体器件中形成用于栅电极图案化的硬掩模的方法。 该方法包括提供待蚀刻并在多晶硅层上形成的多晶硅层，与氧化硅的蚀刻速率相比，具有对氢氟酸的蚀刻速率相对较高的氮化物硬掩模。 然后可以使用硬掩模对多晶硅进行图案化，并且可以使用氢氟酸去除硬掩模。

公开(公告)号：US07109085B2

公开(公告)日：2006-09-19

申请号：US11033912

申请日：2005-01-11

Applicant: Shiang-Bau Wang ,  Li-Te Lin ,  Ming-Ching Chang ,  Ryan Chia-Jen Chen ,  Yuan-Hung Chiu ,  Hun-Jan Tao

Inventor： Shiang-Bau Wang ,  Li-Te Lin ,  Ming-Ching Chang ,  Ryan Chia-Jen Chen ,  Yuan-Hung Chiu ,  Hun-Jan Tao

IPC: H01L21/336

CPC classification number: H01L21/32137 ,  H01L21/31116 ,  H01L21/823828

Abstract: A method for plasma assisted etching of a polysilicon containing gate electrode to reduce or avoid polysilicon notching at a base portion including providing a semiconducting substrate; forming a gate dielectric layer on the semiconducting substrate; forming a polysilicon layer on the gate dielectric; patterning a photoresist layer over the polysilicon layer for etching a gate electrode; carrying out a first plasma assisted etch process to etch through a major thickness portion of the polysilicon layer; carrying out a first inert gas plasma treatment; carrying out a second plasma assisted etch process to include exposing portions of the underlying gate dielectric layer; carrying out a second inert gas plasma treatment; and, carrying out a third plasma assisted etch process to fully expose the underlying gate dielectric layer adjacent either side of the gate electrodes.

Abstract translation: 一种用于等离子体辅助蚀刻含多晶硅栅电极的方法，以减少或避免在包括提供半导体衬底的基极部分处的多晶硅刻蚀; 在所述半导体衬底上形成栅介电层; 在栅极电介质上形成多晶硅层; 在多晶硅层上形成光致抗蚀剂层以蚀刻栅电极; 执行第一等离子体辅助蚀刻工艺以蚀刻通过多晶硅层的主要厚度部分; 进行第一惰性气体等离子体处理; 执行第二等离子体辅助蚀刻工艺以包括暴露下面的栅介电层的部分; 进行第二次惰性气体等离子体处理; 并且执行第三等离子体辅助蚀刻工艺以完全暴露邻近栅电极的任一侧的底层栅介质层。

公开(公告)号：US06900104B1

公开(公告)日：2005-05-31

申请号：US10788754

申请日：2004-02-27

Applicant: Ryan Chia-Jen Chen ,  Fang-Cheng Chen ,  Yuan-Hung Chiu

Inventor： Ryan Chia-Jen Chen ,  Fang-Cheng Chen ,  Yuan-Hung Chiu

IPC: H01L21/311 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/302 ,  H01L21/3205 ,  H01L21/461 ,  H01L21/4763

CPC classification number: H01L29/6653 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/823864 ,  H01L29/6659

Abstract: A method for forming an offset spacer adjacent a CMOS gate structure with improved critical dimension control including providing a substrate that has a gate structure; forming at least one oxide layer over the substrate; forming at least one nitride layer over the at least one oxide layer; dry etching the at least one nitride layer in a first dry etching process to expose a first portion of the at least one oxide layer; carrying out a wet etching process to remove the first portion of the at least one oxide layer; and, dry etching the at least one nitride layer in a second dry etching process to remove the at least one nitride layer leaving a second portion of the at least one oxide layer to form an oxide offset spacer along sidewalls of the gate structure.

Abstract translation: 一种用于在具有改进的临界尺寸控制的CMOS栅极结构附近形成偏移间隔物的方法，包括提供具有栅极结构的衬底; 在衬底上形成至少一个氧化物层; 在所述至少一个氧化物层上形成至少一个氮化物层; 在第一干蚀刻工艺中干蚀刻所述至少一个氮化物层以暴露所述至少一个氧化物层的第一部分; 执行湿蚀刻工艺以去除所述至少一个氧化物层的第一部分; 并且在第二干蚀刻工艺中干蚀刻所述至少一个氮化物层以移除所述至少一个氮化物层，留下所述至少一个氧化物层的第二部分，以在所述栅极结构的侧壁上形成氧化物偏置间隔物。

公开(公告)号：US4484514A

公开(公告)日：1984-11-27

申请号：US471032

申请日：1983-03-01

Applicant: Chia-Jen Chen

Inventor： Chia-Jen Chen

IPC: A47J31/043 ,  A47J31/053

CPC classification number: A47J31/043 ,  A47J31/053

Abstract: A brewing device for either coffee or tea have a water pot bottomed with a base accomodating a heating element and a temperature-sensitive switch connected electrically therewith, by which applying heat to the water pot when being energized and cutting off the source of power at predetermined temperature, and a receiver for coffee grinds or tea to be brewed being disposed by the side of the pot. A U-shaped tube provided between the pot and the receiver having a first leg extended through an first aperture provided in the first lid and a second leg extended through a second aperture provided in the second lid, the former is gas tight sealed with the wall defining the first aperture but on the contrary, there is sufficient opening left between the receiver and the wall defining the second aperture. By such arrangement the water contained in the pot will rise in the first leg till reaching the top of the tube and then descend in the second leg to the receiver by the vapor pressure exerted on the water surface during heating until the water in the pot is exhausted, after de-energized, the brewed beverage in the receiver will return through the bridging means to the pot due to the atmospheric pressure.

Abstract translation: 用于咖啡或茶的冲泡装置具有底部的底部，底部包含加热元件的基座和与其电连接的温度敏感开关，通过该底座在通电时向水壶施加热量并且以预定的方式切断电源 温度以及用于咖啡研磨物或茶的接收器被煮制，由锅的一侧设置。 设置在所述锅和所述接收器之间的U形管具有延伸穿过设置在所述第一盖中的第一孔的第一腿部和延伸穿过设置在所述第二盖中的第二孔的第二腿部，所述第一腿部与所述壁部气密密封 限定第一孔，但相反，在接收器和限定第二孔的壁之间有足够的开口。 通过这种布置，容纳在锅中的水将在第一腿中上升直到到达管的顶部，然后在加热期间通过施加在水面上的蒸汽压力将第二腿下降到接收器，直到锅中的水为 在断电后，由于大气压力，接收器中的冲泡饮料将通过桥接装置返回到锅中。

公开(公告)号：US08912610B2

公开(公告)日：2014-12-16

申请号：US13438451

申请日：2012-04-03

Applicant: Jr Jung Lin ,  Yun-Ju Sun ,  Shih-Hsun Chang ,  Chia-Jen Chen ,  Tomonari Yamamoto ,  Chih-Wei Kuo ,  Meng-Yi Sun ,  Kuo-Chiang Ting

Inventor： Jr Jung Lin ,  Yun-Ju Sun ,  Shih-Hsun Chang ,  Chia-Jen Chen ,  Tomonari Yamamoto ,  Chih-Wei Kuo ,  Meng-Yi Sun ,  Kuo-Chiang Ting

IPC: H01L21/70 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L21/0206 ,  H01L21/02071 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/32136 ,  H01L21/32137 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7848

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate; and a gate stack disposed on the semiconductor substrate. The gate stack includes a high k dielectric material layer, a capping layer disposed on the high k dielectric material layer, and a metal layer disposed on the capping layer. The capping layer and the high k dielectric material layer have a footing structure.

Abstract translation: 本公开提供了一种半导体结构。 半导体结构包括半导体衬底; 以及设置在半导体衬底上的栅极堆叠。 栅极堆叠包括高k电介质材料层，设置在高k电介质材料层上的覆盖层和设置在覆盖层上的金属层。 覆盖层和高k电介质材料层具有基础结构。

公开(公告)号：US08877409B2

公开(公告)日：2014-11-04

申请号：US13451705

申请日：2012-04-20

Applicant: Pei-Cheng Hsu ,  Chih-Tsung Shih ,  Chia-Jen Chen ,  Tsiao-Chen Wu ,  Shinn-Sheng Yu ,  Hsin-Chang Lee ,  Anthony Yen

Inventor： Pei-Cheng Hsu ,  Chih-Tsung Shih ,  Chia-Jen Chen ,  Tsiao-Chen Wu ,  Shinn-Sheng Yu ,  Hsin-Chang Lee ,  Anthony Yen

IPC: G03F1/24

CPC classification number: G03F1/24 ,  G03F1/48 ,  H01L21/0337

Abstract: A reflective mask is described. The mask includes a low thermal expansion material (LTEM) substrate, a conductive layer deposited on a first surface of the LTEM substrate, a stack of reflective multilayers (ML) deposited on a second surface of the LTEM substrate, a capping layer deposited on the stack of reflective ML, a first absorption layer deposited on the first capping layer, a main pattern, and a border ditch. The border ditch reaches to the capping layer, a second absorption layer deposited inside the border ditch, and the second absorption layer contacts the capping layer. In some instances, the border ditch crosses the capping layer and partially enters the reflective multilayer.

Abstract translation: 描述了一种反光罩。 掩模包括低热膨胀材料（LTEM）衬底，沉积在LTEM衬底的第一表面上的导电层，沉积在LTEM衬底的第二表面上的反射多层堆叠（ML），沉积在 堆叠的反射ML，沉积在第一盖层上的第一吸收层，主图案和边界沟。 边界沟到达覆盖层，沉积在边界沟内的第二吸收层，第二吸收层接触覆盖层。 在一些情况下，边界沟穿过覆盖层并部分地进入反射层。

公开(公告)号：US08765330B2

公开(公告)日：2014-07-01

申请号：US13564198

申请日：2012-08-01

Applicant: Chia-Tsung Shih ,  Pei-Chung Hsu ,  Shinn-Sheng Yu ,  Tsiao-Chen Wu ,  Yen-Cheng Lu ,  Shu-Hao Chang ,  Chia-Jen Chen ,  Hsin-Chang Lee ,  Anthony Yen

Inventor： Chia-Tsung Shih ,  Pei-Chung Hsu ,  Shinn-Sheng Yu ,  Tsiao-Chen Wu ,  Yen-Cheng Lu ,  Shu-Hao Chang ,  Chia-Jen Chen ,  Hsin-Chang Lee ,  Anthony Yen

IPC: G03F1/24 ,  G03F1/54

CPC classification number: G03F1/26 ,  G03F1/24

Abstract: A mask and method of fabricating same are disclosed. In an example, a mask includes a substrate, a reflective multilayer coating disposed over the substrate, an Ag2O absorber layer disposed over the reflective multilayer coating, and a tantalum-containing absorber layer disposed over the Ag2O absorber layer. The tantalum-containing absorber layer is disposed over the Ag2O absorber layer outside a mask image region of the mask, such that the mask image region of the mask is free of the tantalum-containing absorber layer. In an example, the tantalum-containing absorber layer is disposed over the Ag2O absorber layer adjacent to the mask image region.

Abstract translation: 公开了一种掩模及其制造方法。 在一个示例中，掩模包括基板，设置在基板上的反射多层涂层，设置在反射多层涂层上的Ag 2 O吸收层，以及设置在Ag 2 O吸收层上的含钽吸收层。 含钽吸收层设置在掩模的掩模图像区域外侧的Ag 2 O吸收体层上，使得掩模的掩模图像区域不含含钽吸收层。 在一个实例中，含钽吸收层设置在与掩模图像区域相邻的Ag 2 O吸收层上。

公开(公告)号：US08748989B2

公开(公告)日：2014-06-10

申请号：US13407507

申请日：2012-02-28

Applicant: Yu Chao Lin ,  Chih-Tang Peng ,  Shun-Hui Yang ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen

Inventor： Yu Chao Lin ,  Chih-Tang Peng ,  Shun-Hui Yang ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen

IPC: H01L21/70

CPC classification number: H01L21/3065 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924

Abstract: The disclosure relates to a fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a major surface; a plurality of first trenches having a first width and extending downward from the substrate major surface to a first height, wherein a first space between adjacent first trenches defines a first fin; and a plurality of second trenches having a second width less than first width and extending downward from the substrate major surface to a second height greater than the first height, wherein a second space between adjacent second trenches defines a second fin.

Abstract translation: 本发明涉及鳍状场效应晶体管（FinFET）。 FinFET的示例性结构包括：包括主表面的衬底; 多个第一沟槽，具有第一宽度并从所述衬底主表面向下延伸到第一高度，其中相邻第一沟槽之间的第一空间限定第一鳍片; 以及多个第二沟槽，其具有小于第一宽度的第二宽度并且从所述衬底主表面向下延伸到大于所述第一高度的第二高度，其中相邻第二沟槽之间的第二空间限定第二鳍片。

公开(公告)号：US08709682B2

公开(公告)日：2014-04-29

申请号：US13369061

申请日：2012-02-08

Applicant: Chia-Jen Chen ,  Anthony Yen ,  Hsin-Chang Lee ,  Sheng-Chi Chin

Inventor： Chia-Jen Chen ,  Anthony Yen ,  Hsin-Chang Lee ,  Sheng-Chi Chin

IPC: G03F1/26

CPC classification number: G03F1/42 ,  G03F1/50 ,  G03F1/84

Abstract: Provided is a method for reducing phase defects on many different types of semiconductor mask blanks. The method includes receiving a semiconductor mask blank substrate, creating alignment marks on the surface of the substrate, performing an inspection of the surface of the substrate to locate a plurality of surface defects, and repairing the plurality of surface defects on the surface of the substrate. A semiconductor mask is also provided that includes a repaired substrate a multilayer stack comprising a plurality of molybdenum and silicon layers, a capping layer, an absorber layer, and in some instances a photoresist layer.

Abstract translation: 提供了一种用于减少许多不同类型的半导体掩模坯料上的相缺陷的方法。 该方法包括：接收半导体掩模空白基板，在基板的表面上产生对准标记，对基板的表面进行检查以定位多个表面缺陷，以及修复基板表面上的多个表面缺陷 。 还提供了一种半导体掩模，其包括修复的衬底，包括多个钼和硅层的多层叠层，覆盖层，吸收层，并且在一些情况下为光致抗蚀剂层。

公开(公告)号：US08651979B2

公开(公告)日：2014-02-18

申请号：US13297237

申请日：2011-11-15

Applicant: Chia-Jen Chen

Inventor： Chia-Jen Chen

IPC: A63B69/00

CPC classification number: A63B69/0097

Abstract: A sports training device includes a base and at least one net frame assembly. The net frame assembly includes a frame mounted detachably to the base, and a net attached to and surrounded by the frame. The net includes a non-elastic mesh area, and an elastic mesh area connecting the non-elastic mesh area to the frame.

Abstract translation: 运动训练装置包括底座和至少一个网框组件。 网框组件包括可拆卸地安装到基座的框架，以及附接到框架并被框架包围的网。 网包括非弹性网格区域和将非弹性网格区域连接到框架的弹性网格区域。