公开(公告)号：US07754574B2

公开(公告)日：2010-07-13

申请号：US11551537

申请日：2006-10-20

Applicant: Douglas D. Coolbaugh ,  Zhong-Xiang He ,  Wolfgang Sauter ,  Barbara A. Waterhouse

Inventor： Douglas D. Coolbaugh ,  Zhong-Xiang He ,  Wolfgang Sauter ,  Barbara A. Waterhouse

IPC: H01L21/44

CPC classification number: H01L24/05 ,  H01L23/5227 ,  H01L24/03 ,  H01L24/45 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48747 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2224/48824 ,  H01L2924/00 ,  H01L2224/48744

Abstract: An RF structure that includes an optimum padset for wire bonding and a high performance inductor that contains relatively thick metal inductor wires, both of which are located atop the final interconnect level of an interconnect structure. Specifically, the RF structure includes a dielectric layer having metal inductor wires of a first thickness and a metal bond pad having a major area of a second thickness located on a surface thereof, wherein the first thickness is greater than the second thickness. In the inventive RF structure, the majority of the metal bond pad is thinned for wire bonding, while maintaining the full metal wire thickness in the other areas of the structure for inductor performance requirements, such as, for example, low resistivity. Methods for fabricating the aforementioned RF structure are also provided.

Abstract translation: RF结构包括用于引线键合的最佳焊盘和包含相对较厚的金属电感器导线的高性能电感器，两者都位于互连结构的最终互连级别的顶部。 具体地，RF结构包括具有第一厚度的金属电感器线和位于其表面上的具有第二厚度的主要面积的金属接合焊盘的电介质层，其中第一厚度大于第二厚度。 在本发明的RF结构中，大部分金属焊盘被减薄以进行引线接合，同时保持结构的其它区域中的全部金属线厚度用于电感器性能要求，例如低电阻率。 还提供了制造上述RF结构的方法。

公开(公告)号：US07714412B2

公开(公告)日：2010-05-11

申请号：US10711144

申请日：2004-08-27

Applicant: Douglas D. Coolbaugh ,  Douglas B. Hershberger ,  Robert M. Rassel

Inventor： Douglas D. Coolbaugh ,  Douglas B. Hershberger ,  Robert M. Rassel

IPC: H01L29/93

CPC classification number: H01L29/93 ,  H01L29/94

Abstract: The present invention provides a varactor that has increased tunability and a high quality factor Q as well as a method of fabricating the varactor. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes providing a structure that includes a semiconductor substrate of a first conductivity type and optionally a subcollector or isolation well (i.e., doped region) of a second conductivity type located below an upper region of the substrate, the first conductivity type is different from said second conductivity type. Next, a plurality of isolation regions are formed in the upper region of the substrate and then a well region is formed in the upper region of the substrate. In some cases, the doped region is formed at this point of the inventive process. The well region includes outer well regions of the second conductivity type and an inner well region of the first conductivity type. Each well of said well region is separated at an upper surface by an isolation region. A field effect transistor having at least a gate conductor of the first conductivity type is then formed above the inner well region.

Abstract translation: 本发明提供一种具有增加的可调性和高品质因数Q的变容二极管以及制造变容二极管的方法。 本发明的方法可以集成到常规的CMOS处理方案中，或者被整合到常规的BiCMOS处理方案中。 该方法包括提供包括第一导电类型的半导体衬底和位于衬底的上部区域下方的第二导电类型的子集电极或隔离阱（即，掺杂区）的结构，第一导电类型不同于 所述第二导电类型。 接下来，在基板的上部区域形成多个隔离区域，然后在基板的上部区域形成阱区域。 在一些情况下，在本发明方法的这一点形成掺杂区域。 阱区包括第二导电类型的外阱区和第一导电类型的内阱区。 所述阱区的每个阱在上表面被隔离区分开。 然后形成至少具有第一导电类型的栅极导体的场效应晶体管，并在内部阱区域的上方形成。

公开(公告)号：US07659176B2

公开(公告)日：2010-02-09

申请号：US11627408

申请日：2007-01-26

Applicant: Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Richard J. Rassel ,  Robert M. Rassel

Inventor： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Richard J. Rassel ,  Robert M. Rassel

IPC: H01L21/20

CPC classification number: H01L28/20

Abstract: Tunable TCR resistors incorporated into integrated circuits and a method fabricating the tunable TCR resistors. The tunable TCR resistors including two or more resistors of two or more different materials having opposite polarity and different magnitude TCRs, the same polarity and different magnitude TCRs or having opposite polarity and about the same TCRs.

Abstract translation: 整合在集成电路中的可调TCR电阻和制造可调TCR电阻的方法。 可调TCR电阻器包括具有相反极性和不同幅度TCR，相同极性和不同幅度TCR或具有相反极性和大约相同TCR的两种或更多种不同材料的两个或更多个电阻器。

公开(公告)号：US07479439B2

公开(公告)日：2009-01-20

申请号：US11737844

申请日：2007-04-20

Applicant: Douglas D. Coolbaugh ,  Zhong-Xiang He ,  Robert M. Rassel ,  Richard J. Rassel ,  Stephen A. St Onge

Inventor： Douglas D. Coolbaugh ,  Zhong-Xiang He ,  Robert M. Rassel ,  Richard J. Rassel ,  Stephen A. St Onge

IPC: H01L21/8244

CPC classification number: H01L29/94

Abstract: A semiconductor-insulator-silicide (SIS) capacitor is formed by depositing a thin silicon containing layer on a salicide mask dielectric layer, followed by lithographic patterning of the stack and metallization of the thin silicon containing layer and other exposed semiconductor portions of a semiconductor substrate. The thin silicon containing layer is fully reacted during metallization and consequently converted to a silicide alloy layer, which is a first electrode of a capacitor. The salicide mask dielectric layer is the capacitor dielectric. The second electrode of the capacitor may be a doped polycrystalline silicon containing layer, a doped single crystalline semiconductor region, or another doped polycrystalline silicon containing layer disposed on the doped polycrystalline silicon containing layer. The SIS insulator may further comprise other dielectric layers and conductive layers to increase capacitance per area.

Abstract translation: 半导体绝缘体硅化物（SIS）电容器是通过在硅化物掩模介电层上沉积薄硅层而形成的，随后叠层的平版印刷图案化以及薄硅层和半导体衬底的其它暴露的半导体部分的金属化 。 含硅薄层在金属化期间完全反应，因此转化为硅化物合金层，其是电容器的第一电极。 硅化物掩模介电层是电容器电介质。 电容器的第二电极可以是掺杂的多晶硅含硅层，掺杂的单晶半导体区域或设置在掺杂的多晶硅含硅层上的另一掺杂的多晶硅含硅层。 SIS绝缘体还可以包括其它电介质层和导电层，以增加每面积的电容。

公开(公告)号：US20080185684A1

公开(公告)日：2008-08-07

申请号：US12098479

申请日：2008-04-07

Applicant: Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Ebenezer Eshun ,  Vincent J. McGahay ,  Anthony K. Stamper ,  Kunal Vaed

Inventor： Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Ebenezer Eshun ,  Vincent J. McGahay ,  Anthony K. Stamper ,  Kunal Vaed

IPC: H01L29/92

CPC classification number: H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for integrating the formation of metal-insulator-metal (MIM) capacitors within dual damascene processing includes forming a lower interlevel dielectric (ILD) layer having a lower capacitor electrode and one or more lower metal lines therein, the ILD layer having a first dielectric capping layer formed thereon. An upper ILD layer is formed over the lower ILD layer, and a via and upper line structure are defined within the upper ILD layer. The via and upper line structure are filled with a planarizing layer, followed by forming and patterning a resist layer over the planarizing layer. An upper capacitor electrode structure is defined in the upper ILD layer corresponding to a removed portion of the resist. The via, upper line structure and upper capacitor electrode structure are filled with conductive material, wherein a MIM capacitor is defined by the lower capacitor electrode, first dielectric capping layer and upper capacitor electrode structure.

公开(公告)号：US07310036B2

公开(公告)日：2007-12-18

申请号：US10905546

申请日：2005-01-10

Applicant: Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Terence B. Hook ,  Robert M. Rassel ,  Edmund J. Sprogis ,  Anthony K Stamper ,  William J. Murphy

Inventor： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Terence B. Hook ,  Robert M. Rassel ,  Edmund J. Sprogis ,  Anthony K Stamper ,  William J. Murphy

IPC: H01C1/08

CPC classification number: H01C7/1013 ,  H01C1/084 ,  H01L2924/0002 ,  Y10T29/49083 ,  Y10T29/49085 ,  Y10T29/49099 ,  Y10T29/49144 ,  Y10T29/49147 ,  H01L2924/00

Abstract: A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.

Abstract translation: 提供带散热片的电阻。 散热器包括具有导热性高的金属或其它热导体的导电路径。 为了避免使用热导体将电阻器短路接地，在热导体和电阻体之间插入有一层薄导电电绝缘体。 因此，电阻器可承载大量的电流，因为高导电性热导体将热量从电阻器传导到散热器。 除了降低寄生电容和其他寄生电效应之外，提供各种配置的导热体和散热片，提供良好的导热性能，这将降低电阻器的高频响应。

公开(公告)号：US07239006B2

公开(公告)日：2007-07-03

申请号：US10709115

申请日：2004-04-14

Applicant: Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Robert M. Rassel ,  Anthony K. Stamper

Inventor： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Robert M. Rassel ,  Anthony K. Stamper

IPC: H01L29/00

CPC classification number: H01C17/267

Abstract: A structure for resistors and the method for tuning the same. The resistor comprises an electrically conducting region coupled to a liner region. Both the electrically conducting region and the liner region are electrically coupled to first and second contact regions. A voltage difference is applied between the first and second contact regions. As a result, a current flows between the first and second contact regions in the electrically conducting region. The voltage difference and the materials of the electrically conducting region and the liner region are such that electromigration occurs only in the electrically conducting region. As a result, a void region within the electrically conducting region expands in the direction of the flow of the charged particles constituting the current. Because the resistor loses a conducting portion of the electrically conducting region to the void region, the resistance of the resistor is increased (i.e., tuned).

Abstract translation: 电阻器结构及其调谐方法。 电阻器包括耦合到衬垫区域的导电区域。 导电区域和衬里区域都电耦合到第一和第二接触区域。 在第一和第二接触区域之间施加电压差。 结果，电流在导电区域中的第一和第二接触区域之间流动。 导电区域和衬垫区域的电压差和材料使得电迁移仅在导电区域中发生。 结果，导电区域内的空隙区域在构成电流的带电粒子的流动方向上膨胀。 因为电阻器将导电区域的导电部分损失到空隙区域，电阻器的电阻增加（即调谐）。

公开(公告)号：US07170181B2

公开(公告)日：2007-01-30

申请号：US10707064

申请日：2003-11-19

Applicant: Douglas D. Coolbaugh ,  Zhong-Xiang He ,  Wolfgang Sauter ,  Barbara A. Waterhouse

Inventor： Douglas D. Coolbaugh ,  Zhong-Xiang He ,  Wolfgang Sauter ,  Barbara A. Waterhouse

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/05 ,  H01L23/5227 ,  H01L24/03 ,  H01L24/45 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48747 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2224/48824 ,  H01L2924/00 ,  H01L2224/48744

Abstract: An RF structure that includes an optimum padset for wire bonding and a high performance inductor that contains relatively thick metal inductor wires, both of which are located atop the final interconnect level of an interconnect structure. Specifically, the RF structure includes a dielectric layer having metal inductor wires of a first thickness and a metal bond pad having a major area of a second thickness located on a surface thereof, wherein the first thickness is greater than the second thickness. In the inventive RF structure, the majority of the metal bond pad is thinned for wire bonding, while maintaining the full metal wire thickness in the other areas of the structure for inductor performance requirements, such as, for example, low resistivity. Methods for fabricating the aforementioned RF structure are also provided.

Abstract translation: RF结构包括用于引线键合的最佳焊盘和包含相对较厚的金属电感器导线的高性能电感器，两者都位于互连结构的最终互连级别的顶部。 具体地，RF结构包括具有第一厚度的金属电感器线和位于其表面上的具有第二厚度的主要面积的金属接合焊盘的电介质层，其中第一厚度大于第二厚度。 在本发明的RF结构中，大部分金属焊盘被减薄以进行引线接合，同时保持结构的其它区域中的全部金属线厚度用于电感器性能要求，例如低电阻率。 还提供了制造上述RF结构的方法。

公开(公告)号：US07112535B2

公开(公告)日：2006-09-26

申请号：US10605439

申请日：2003-09-30

Applicant: Douglas D. Coolbaugh ,  Heidi L. Greer ,  Robert M. Rassel

Inventor： Douglas D. Coolbaugh ,  Heidi L. Greer ,  Robert M. Rassel

IPC: H01L21/302

CPC classification number: H01L27/0738 ,  H01L27/0802 ,  H01L28/20

Abstract: A process is disclosed for fabricating precision polysilicon resistors which more precisely control the tolerance of the sheet resistivity of the produced polysilicon resistors. The process generally includes performing an emitter/FET activation rapid thermal anneal (RTA) on a wafer having partially formed polysilicon resistors, followed by steps of depositing a protective dielectric layer on the polysilicon, implanting a dopant through the protective dielectric layer into the polysilicon to define the resistance of the polysilicon resistors, and forming a silicide.

Abstract translation: 公开了一种制造精密多晶硅电阻器的方法，其更精确地控制所产生的多晶硅电阻器的薄层电阻率的公差。 该方法通常包括在具有部分形成的多晶硅电阻器的晶片上执行发射极/ FET激活快速热退火（RTA），随后是在多晶硅上沉积保护性介电层的步骤，将掺杂剂通过保护电介质层注入到多晶硅中 限定多晶硅电阻器的电阻，并形成硅化物。

公开(公告)号：US06958506B2

公开(公告)日：2005-10-25

申请号：US10688508

申请日：2003-10-17

Applicant: Evgeni P. Gousev ,  Harald F. Okorn-Schmidt ,  Arne W. Ballantine ,  Douglas A. Buchanan ,  Eduard A. Cartier ,  Douglas D. Coolbaugh

Inventor： Evgeni P. Gousev ,  Harald F. Okorn-Schmidt ,  Arne W. Ballantine ,  Douglas A. Buchanan ,  Eduard A. Cartier ,  Douglas D. Coolbaugh

IPC: H01L29/73 ,  H01L21/02 ,  H01L21/28 ,  H01L21/331 ,  H01L21/822 ,  H01L21/8222 ,  H01L21/8234 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L29/51 ,  H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L27/0629 ,  H01L27/0635 ,  H01L27/0805 ,  H01L28/55 ,  H01L28/60 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/94

Abstract: Methods of forming front-end-of the line (FEOL) capacitors such as polysilicon-polysilicon capacitors and metal-insulator-silicon capacitors are provided that are capable of incorporating a high-dielectric constant (k of greater than about 8) into the capacitor structure. The inventive methods provide high capacitance/area devices with low series resistance of the top and bottom electrodes for high frequency responses. The inventive methods provide a significant reduction in chip size, especially in analog and mixed-signal applications where large areas of capacitance are used.

Abstract translation: 提供了形成前端的方法（FEOL）电容器，例如多晶硅 - 多晶硅电容器和金属 - 绝缘体 - 硅电容器，其能够将高介电常数（k大于约8）并入电容器 结构体。 本发明的方法提供了用于高频响应的顶部和底部电极具有低串联电阻的高电容/面积器件。 本发明的方法提供了芯片尺寸的显着降低，特别是在使用大面积电容的模拟和混合信号应用中。