公开(公告)号：US20070059923A1

公开(公告)日：2007-03-15

申请号：US11445458

申请日：2006-06-02

申请人： Hyo-jong Lee ,  Ui-hyoung Lee ,  Hong-jae Shin ,  Nae-in Lee ,  Soo-geun Lee

发明人： Hyo-jong Lee ,  Ui-hyoung Lee ,  Hong-jae Shin ,  Nae-in Lee ,  Soo-geun Lee

IPC分类号： H01L21/4763

CPC分类号： H01L21/76885 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76843

摘要： Methods of fabricating an interconnection line in a semiconductor device and a semiconductor device including such an interconnection line. The method involves forming a lower interconnection line on a semiconductor substrate, forming a mold pattern that defines an opening through which the lower interconnection line is exposed, filling the opening with a conductive material to form a via, removing the mold pattern to make the via remain on the lower interconnection line, forming an interlevel dielectric (ILD) layer that covers the lower interconnection line and the via, patterning the ILD layer, exposing the via, forming a trench that defines a region in which an interconnection line is to be formed, and filling the trench to fabricate a damascene interconnection line connected to the via.

摘要翻译： 在半导体器件中制造互连线的方法和包括这种互连线的半导体器件。 该方法包括在半导体衬底上形成下部互连线，形成限定下部互连线暴露的开口的模具图案，用导电材料填充开口以形成通孔，去除模具图案以形成通孔 保持在下互连线上，形成覆盖下互连线和通孔的层间电介质（ILD）层，图案化ILD层，暴露通孔，形成限定要形成互连线的区域的沟槽 ，并填充沟槽以制造连接到通孔的镶嵌互连线。

公开(公告)号：US20060110915A1

公开(公告)日：2006-05-25

申请号：US11328954

申请日：2006-01-09

申请人： Hong-Jae Shin

发明人： Hong-Jae Shin

IPC分类号： H01L21/4763

CPC分类号： H01L24/05 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05567 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2224/05552

摘要： A low-k dielectric film is formed on an entire surface of a substrate having a pad region and a circuit region. A resist pattern is formed on the low-k dielectric film, and an opening is formed in the low-k dielectric film of the pad region using the resist pattern as a mask. A silicon oxide film having strength higher than the low-k dielectric film is formed in the opening using liquid-phase deposition method. Wirings are formed in the silicon oxide film of the pad region and in the low-k dielectric film of the circuit region using damascene method.

摘要翻译： 在具有焊盘区域和电路区域的衬底的整个表面上形成低k电介质膜。 在低k电介质膜上形成抗蚀剂图案，并且使用抗蚀剂图案作为掩模，在焊盘区域的低k电介质膜中形成开口。 使用液相沉积法在开口中形成强度高于低k电介质膜的氧化硅膜。 使用镶嵌方法，在焊盘区域的氧化硅膜和电路区域的低k电介质膜中形成布线。

公开(公告)号：US07015589B2

公开(公告)日：2006-03-21

申请号：US10806341

申请日：2004-03-23

申请人： Hong-Jae Shin

发明人： Hong-Jae Shin

IPC分类号： H01L29/40 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L24/05 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05567 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2224/05552

摘要： A low-k dielectric film is formed on an entire surface of a substrate having a pad region and a circuit region. A resist pattern is formed on the low-k dielectric film, and an opening is formed in the low-k dielectric film of the pad region using the resist pattern as a mask. A silicon oxide film having strength higher than the low-k dielectric film is formed in the opening by liquid-phase deposition. Wirings are formed in the silicon oxide film of the pad region and in the low-k dielectric film of the circuit region using the damascene method.

摘要翻译： 在具有焊盘区域和电路区域的衬底的整个表面上形成低k电介质膜。 在低k电介质膜上形成抗蚀剂图案，并且使用抗蚀剂图案作为掩模，在焊盘区域的低k电介质膜中形成开口。 通过液相沉积在开口中形成强度高于低k电介质膜的氧化硅膜。 使用镶嵌方法，在焊盘区域的氧化硅膜和电路区域的低k电介质膜中形成布线。

公开(公告)号：US20060009065A1

公开(公告)日：2006-01-12

申请号：US11174864

申请日：2005-07-05

申请人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jeong-Hoon Ahn ,  Seung-Man Choi ,  Byung-Jun Oh ,  Yoon-Hae Kim

发明人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jeong-Hoon Ahn ,  Seung-Man Choi ,  Byung-Jun Oh ,  Yoon-Hae Kim

IPC分类号： H01R4/24

CPC分类号： H01L23/5223 ,  H01L21/76808 ,  H01L21/76877 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of manufacturing a semiconductor device, a first insulation layer on the substrate is patterned to form a first opening having a first width. A lower electrode is formed along an inner contour of the first opening. A second insulation layer on the first insulation layer is patterned to form a second opening that has a second width greater than the first width and is connected to the first opening with a stepped portion. A dielectric layer is formed on the lower electrode in the first opening, a sidewall of the second opening and a first stepped portion between the first insulation layer and the second insulation layer, so that the electrode layer is covered with the dielectric layer. An upper electrode is formed on the dielectric layer. Accordingly, a leakage current between the lower and upper electrodes is suppressed.

摘要翻译： 在制造半导体器件的方法中，将衬底上的第一绝缘层图案化以形成具有第一宽度的第一开口。 沿着第一开口的内轮廓形成下电极。 第一绝缘层上的第二绝缘层被图案化以形成具有大于第一宽度的第二宽度的第二开口，并且连接到具有阶梯部分的第一开口。 在第一开口的下电极，第二开口的侧壁和第一绝缘层与第二绝缘层之间的第一台阶部分上形成电介质层，使电极层被电介质层覆盖。 在电介质层上形成上电极。 因此，抑制了下电极和上电极之间的漏电流。

公开(公告)号：US20060003574A1

公开(公告)日：2006-01-05

申请号：US11099534

申请日：2005-04-06

申请人： Jae-Hak Kim ,  Kyoung-Woo Lee ,  Hong-Jae Shin ,  Young-Joon Moon ,  Seo-Woo Nam

发明人： Jae-Hak Kim ,  Kyoung-Woo Lee ,  Hong-Jae Shin ,  Young-Joon Moon ,  Seo-Woo Nam

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808

摘要： A method of forming a via contact structure using a dual damascene process is disclosed. According to one embodiment a sacrificial layer is formed on an insulating interlayer during the formation of a preliminary via hole. The sacrificial layer has the same composition as a layer filling the preliminary via hole in a subsequent trench formation process. The sacrificial layer and the layer filling the preliminary via hole are simultaneously removed after the trench formation process is carried out. According to another embodiment, a thin capping oxide layer is formed on an insulating interlayer during the formation of a preliminary via hole. The thin capping oxide layer is removed together with a sacrificial layer after a trench formation process is carried out.

摘要翻译： 公开了一种使用双镶嵌工艺形成通孔接触结构的方法。 根据一个实施例，在形成预通孔期间，在绝缘中间层上形成牺牲层。 牺牲层具有与随后的沟槽形成过程中填充预通孔的层相同的组成。 在进行沟槽形成处理之后，同时去除牺牲层和填充预通孔的层。 根据另一实施例，在形成预通孔期间，在绝缘中间层上形成薄封盖氧化物层。 在进行沟槽形成处理之后，薄层氧化物层与牺牲层一起被去除。

公开(公告)号：US20050176236A1

公开(公告)日：2005-08-11

申请号：US11049730

申请日：2005-02-04

申请人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jae-Hak Kim ,  Young-Jin Wee ,  Seung-Jin Lee ,  Ki-Kwan Park

发明人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jae-Hak Kim ,  Young-Jin Wee ,  Seung-Jin Lee ,  Ki-Kwan Park

IPC分类号： H01L21/3205 ,  H01L21/02 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/02063 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76835

摘要： The present invention discloses a method of fabricating interconnection lines for a semiconductor device. The method includes forming an interlayer insulating layer on a semiconductor substrate. A via hole is formed through the interlayer insulating layer. A via filling material is formed to fill the via hole. A photoresist pattern is formed on the via filling material. The via filling material and the interlayer insulating layer are anisotropically etched using the photoresist pattern as an etch mask to form a trench. A residual portion of the via filling material is removed using two wet etch processes. After removing the residual portion of the via filling material, a conductive layer pattern is formed in the via hole and the trench.

摘要翻译： 本发明公开了一种制造用于半导体器件的互连线的方法。 该方法包括在半导体衬底上形成层间绝缘层。 通过层间绝缘层形成通孔。 形成通孔填充材料以填充通孔。 在通孔填充材料上形成光致抗蚀剂图案。 使用光致抗蚀剂图案作为蚀刻掩模对通孔填充材料和层间绝缘层进行各向异性蚀刻以形成沟槽。 使用两次湿式蚀刻工艺去除通孔填充材料的剩余部分。 在去除通孔填充材料的剩余部分之后，在通孔和沟槽中形成导电层图案。

公开(公告)号：US20050161821A1

公开(公告)日：2005-07-28

申请号：US11028515

申请日：2005-01-04

申请人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jae-Hak Kim ,  Young-Jin Wee ,  Seung-Jin Lee ,  Ki-Kwan Park

发明人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jae-Hak Kim ,  Young-Jin Wee ,  Seung-Jin Lee ,  Ki-Kwan Park

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L21/4763 ,  H01L21/44 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L21/76808 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76829

摘要： Methods for forming an interconnection line and interconnection line structures are disclosed. The method includes forming an interlayer insulating layer on a semiconductor substrate, wherein the interlayer insulating layer is formed of a carbon-doped low-k dielectric layer. An oxidation barrier layer is formed on the interlayer insulating layer. An oxide capping layer is formed on the oxidation barrier layer. A via hole is in the oxide capping layer, the oxidation barrier, and the interlayer insulating layer. A conductive layer pattern is formed within the via hole.

摘要翻译： 公开了形成互连线和互连线结构的方法。 该方法包括在半导体衬底上形成层间绝缘层，其中层间绝缘层由碳掺杂的低k电介质层形成。 在层间绝缘层上形成氧化阻隔层。 在氧化阻挡层上形成氧化物覆盖层。 通孔位于氧化物覆盖层，氧化阻挡层和层间绝缘层中。 导电层图案形成在通孔内。

公开(公告)号：US06483162B2

公开(公告)日：2002-11-19

申请号：US09785442

申请日：2001-02-20

申请人： Dong-chul Kwon ,  Young-jin Wee ,  Hong-jae Shin ,  Sung-jin Kim

发明人： Dong-chul Kwon ,  Young-jin Wee ,  Hong-jae Shin ,  Sung-jin Kim

IPC分类号： H01L2348

CPC分类号： H01L21/76831 ,  H01L21/76802 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having improved metal line structure has a first dielectric layer formed on a semiconductor substrate, a metal film pattern formed on the first dielectric layer, an interface protection layer on the metal film pattern, and a second dielectric layer on the interface protection layer, wherein the second dielectric layer contains a reactive material, e.g., fluorine, which is prevented by the interface protection layer from diffusing to the metal film pattern and reacting with the metal in the metal film pattern to form a damage film, e.g., metal fluoride, which is a highly resistive material that, if formed on the semiconductor device, would reduce the reliability of the metal film pattern and thus reduce the reliability of the semiconductor device as a whole.

摘要翻译： 具有改进的金属线结构的半导体器件具有形成在半导体衬底上的第一电介质层，形成在第一介电层上的金属膜图案，金属膜图案上的界面保护层和界面保护层上的第二介电层 其中所述第二电介质层包含反应性材料，例如氟，所述反应性材料被界面保护层阻止扩散到金属膜图案并与金属膜图案中的金属反应以形成损伤膜，例如金属氟化物 其是高电阻材料，如果形成在半导体器件上，则会降低金属膜图案的可靠性，从而降低半导体器件整体的可靠性。

公开(公告)号：US06277764B1

公开(公告)日：2001-08-21

申请号：US09224560

申请日：1998-12-30

申请人： Hong-jae Shin ,  Hee-sook Park ,  Sung-jin Kim

发明人： Hong-jae Shin ,  Hee-sook Park ,  Sung-jin Kim

IPC分类号： H01L2131

CPC分类号： H01L21/02131 ,  H01L21/02134 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/31053 ,  H01L21/3124 ,  H01L21/3127 ,  H01L21/314 ,  H01L21/31629 ,  H01L21/76801 ,  H01L21/76835 ,  H01L21/76837

摘要： A method of forming an interlayer dielectric layer of a semiconductor device and an interlayer dielectric layer using the same. By the method, a semiconductor substrate formed metal interconnect lines thereon is provided, a first insulating layer of a low dielectric material is formed on the semiconductor substrate, by a spin coating, and a second insulating layer of a low dielectric material is formed on the first insulating layer, by the high density plasma chemical vapor deposition (CVD). The second insulating layer is planarized through a chemical mechanical polishing (CMP) process.

摘要翻译： 一种形成半导体器件的层间电介质层的方法和使用其的层间电介质层。 通过该方法，在其上形成有金属互连线的半导体衬底，通过旋涂在半导体衬底上形成低介电材料的第一绝缘层，并且在第二绝缘层上形成低电介质材料的第二绝缘层 第一绝缘层，通过高密度等离子体化学气相沉积（CVD）。 通过化学机械抛光（CMP）工艺对第二绝缘层进行平面化处理。

公开(公告)号：US08816944B2

公开(公告)日：2014-08-26

申请号：US11453529

申请日：2006-06-15

申请人： Tae-Whan Kim ,  Kae-Dal Kwack ,  Hong-Jae Shin

发明人： Tae-Whan Kim ,  Kae-Dal Kwack ,  Hong-Jae Shin

IPC分类号： G09G3/30

CPC分类号： G09G3/3283 ,  G09G3/2014 ,  G09G3/3216 ,  G09G2320/0233

摘要： A display device, which includes a plurality of pixels; a data driver for outputting data signals to the pixels; a bias current outputting unit for outputting a bias current having a predetermined magnitude; a plurality of driving current outputting units for outputting driving currents to the pixels; and a first switch connected between the bias current outputting unit and the driving current outputting units for selecting one of the driving current outputting units to connect to the bias current outputting unit, wherein the magnitudes of the driving currents are substantially the same as a magnitude of the bias current.

摘要翻译： 一种显示装置，包括多个像素; 用于将数据信号输出到像素的数据驱动器; 偏置电流输出单元，用于输出具有预定大小的偏置电流; 多个驱动电流输出单元，用于向像素输出驱动电流; 以及第一开关，连接在所述偏置电流输出单元和所述驱动电流输出单元之间，用于选择所述驱动电流输出单元中的一个连接到所述偏置电流输出单元，其中所述驱动电流的大小基本上与 偏置电流。