公开(公告)号：US20070085558A1

公开(公告)日：2007-04-19

申请号：US11638846

申请日：2006-12-13

申请人： Irfan Rahim ,  Peter McElheny ,  John Costello

发明人： Irfan Rahim ,  Peter McElheny ,  John Costello

IPC分类号： G01R31/26

CPC分类号： G11C5/147 ,  H03K19/177

摘要： The present invention optimizes the performance of integrated circuits by adjusting the circuit operating voltage using feedback on process/product parameters. To determine a desired value for the operating voltage of an integrated circuit, a preferred embodiment provides for on-wafer probing of one or more reference circuit structures to measure at least one electrical or operational parameter of the one or more reference circuit structures; determining an adjusted value for the operating voltage based on the measured parameter; and establishing the adjusted value as the desired value for the operating voltage. The reference circuit structures may comprise process control monitor structures or structures in other integrated circuits fabricated in the same production run. In an alternative embodiment, the one or more parameters are directly measured from the integrated circuit whose operating voltage is being adjusted

摘要翻译： 本发明通过使用对过程/产品参数的反馈来调节电路工作电压来优化集成电路的性能。 为了确定集成电路的工作电压的期望值，优选实施例提供一个或多个参考电路结构的片上探测，以测量一个或多个参考电路结构的至少一个电或操作参数; 基于所测量的参数确定所述工作电压的调整值; 并将调整后的值建立为工作电压的期望值。 参考电路结构可以包括在相同生产运行中制造的其它集成电路中的过程控制监视器结构或结构。 在替代实施例中，一个或多个参数是直接从其工作电压正被调整的集成电路测量的

公开(公告)号：US07142009B1

公开(公告)日：2006-11-28

申请号：US10942692

申请日：2004-09-15

申请人： Jeffrey Watt ,  Irfan Rahim

发明人： Jeffrey Watt ,  Irfan Rahim

IPC分类号： H03K19/173 ,  G06F1/26

CPC分类号： H03K19/0008 ,  H03K19/177

摘要： Adaptive regulated power supply voltages are applied to programmable logic integrated circuits. Control circuitry in a programmable logic IC generates control signals that are transmitted to an external voltage regulator. The voltage regulator generates one or more power supply voltages in response to the control signals. The values of control signals determine the target values of the supply voltages. The control circuitry can adapt the power supply voltages to compensate for temperature and process variations on the IC. The power supply voltages can be programmed by a manufacturer or by a user to achieve desired target values. The control circuitry can also put a programmable logic IC into a sleep mode by dropping the high supply voltage to a low value to reduce power consumption during periods of low usage.

摘要翻译： 自适应稳压电源电压被施加到可编程逻辑集成电路。 可编程逻辑IC中的控制电路产生传输到外部电压调节器的控制信号。 电压调节器响应于控制信号产生一个或多个电源电压。 控制信号的值确定电源电压的目标值。 控制电路可以调节电源电压以补偿IC上的温度和工艺变化。 电源电压可以由制造商或用户编程以实现期望的目标值。 控制电路还可以通过将高电源电压降低到低值来将可编程逻辑IC置于睡眠模式，以在低使用期间降低功耗。

公开(公告)号：US07139997B1

公开(公告)日：2006-11-21

申请号：US10844034

申请日：2004-05-11

申请人： Irfan Rahim ,  Bradley Jensen ,  Girish Venkitachalam ,  Hugh Sung-Ki O ,  Susan Falk ,  Priya Selvaraj

发明人： Irfan Rahim ,  Bradley Jensen ,  Girish Venkitachalam ,  Hugh Sung-Ki O ,  Susan Falk ,  Priya Selvaraj

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： Disclosed is a method for checking the operation of an IC mask generation algorithm in which at least a first identifier of the mask generation algorithm is associated with at least a first symbol that is not associated with generating a functional IC feature. The first symbol has a predetermined size and a predetermined shape. A predetermined location on a mask is also associated with the first symbol. A mask diagram on the mask is generated at least partially at the first predetermined location. The size and shape of the mask diagram is then compared with at least a portion of the first predetermined size and the first predetermined shape of the first symbol.

摘要翻译： 公开了一种用于检查IC掩模生成算法的操作的方法，其中至少掩模生成算法的第一标识符与至少与生成功能IC特征相关联的第一符号相关联。 第一符号具有预定尺寸和预定形状。 掩模上的预定位置也与第一符号相关联。 至少部分地在第一预定位置处产生掩模上的掩模图。 然后将掩模图的尺寸和形状与第一符号的第一预定尺寸和第一预定形状的至少一部分进行比较。

公开(公告)号：US07129745B2

公开(公告)日：2006-10-31

申请号：US10865402

申请日：2004-06-10

申请人： David Lewis ,  Vaughn Betz ,  Irfan Rahim ,  Peter McElheny ,  Yow-Juang W. Liu ,  Bruce Pedersen

发明人： David Lewis ,  Vaughn Betz ,  Irfan Rahim ,  Peter McElheny ,  Yow-Juang W. Liu ,  Bruce Pedersen

IPC分类号： H03K19/173

CPC分类号： G06F17/5054 ,  H03K5/133 ,  H03K19/00369 ,  H03K2005/00058 ,  H03K2005/00156 ,  H03K2217/0018

摘要： A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.

公开(公告)号：US20060237784A1

公开(公告)日：2006-10-26

申请号：US11114455

申请日：2005-04-25

申请人： Irfan Rahim ,  Yow-Juang Liu ,  Jeffrey Watt

发明人： Irfan Rahim ,  Yow-Juang Liu ,  Jeffrey Watt

IPC分类号： H01L29/76

CPC分类号： H01L27/0203 ,  H01L21/823857 ,  H01L27/0922 ,  H01L27/11807 ,  H01L27/11898 ,  Y10S257/903

摘要： An integrated circuit having an enhanced on-off swing for pass gate transistors is provided. The integrated circuit includes a core region that includes core transistors and pass gate transistors. The core transistors have a gate oxide associated with a first thickness, the pass transistors having a gate oxide associated with a thickness that is less than the first thickness. In one embodiment, the material used for the gate oxide of the pass gate transistors has a dielectric constant that is greater than four, while the material used for the gate oxide of the core transistors has a dielectric constant that is less than or equal to four. A method for manufacturing an integrated circuit is also provided.

摘要翻译： 提供了一种具有用于通过栅极晶体管的增强的通断摆幅的集成电路。 集成电路包括具有核心晶体管和栅极晶体管的核心区域。 核心晶体管具有与第一厚度相关的栅极氧化物，所述通过晶体管具有与小于第一厚度的厚度相关联的栅极氧化物。 在一个实施例中，用于栅极晶体管的栅极氧化物的材料具有大于4的介电常数，而用于核心晶体管的栅极氧化物的材料具有小于或等于4的介电常数 。 还提供了一种用于制造集成电路的方法。

公开(公告)号：US06963503B1

公开(公告)日：2005-11-08

申请号：US10618280

申请日：2003-07-11

申请人： Irfan Rahim ,  Veenu Shekhar

发明人： Irfan Rahim ,  Veenu Shekhar

IPC分类号： G11C16/04

CPC分类号： G11C16/0441 ,  G11C2216/10 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11558

摘要： An EEPROM cell with reduced cell size and improved circuit performance includes a high-voltage (HV) capacitor, a low-voltage (LV) read path, and an HV write path, wherein either the HV capacitor is placed between the LV read path and the HV write path or the HV write path is placed between the LV read path and the HV capacitor. The EEPROM cell also includes a native floating-gate (FG) transistor in the LV read path. Using a native FG transistor in the LV read path results in further reduction in the cell size and improved circuit performance of the EEPROM cell.

摘要翻译： 具有减小的单元尺寸和改进的电路性能的EEPROM单元包括高压（HV）电容器，低电压（LV）读取路径和HV写入路径，其中HV电容器放置在LV读取路径和 HV写入路径或HV写入路径位于LV读取路径和HV电容器之间。 EEPROM单元还包括LV读取路径中的原生浮栅（FG）晶体管。 在LV读取路径中使用本机FG晶体管导致EEPROM单元的单元尺寸的进一步减小和电路性能的提高。

公开(公告)号：US6069382A

公开(公告)日：2000-05-30

申请号：US22222

申请日：1998-02-11

申请人： Irfan Rahim

发明人： Irfan Rahim

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L29/7883 ,  H01L21/28273 ,  H01L29/42324

摘要： A non-volatile memory cell includes a floating gate having a bottom surface in contact with a tunnel layer formed on the substrate, a top surface, and sidewall surfaces oriented along the bitline direction and along the wordline direction of the memory cell. A dielectric layer covers at least a portion of the top surface and covers at least a portion of the surfaces oriented along the bitline and wordline directions. A control gate overlaps the floating gate over substantially all of its surface area. A plurality of self-aligned sidewall spacers are provided, disposed against at least the dielectric layer and the control gate sidewalls. By overlapping the control gate over the floating gate, a greater surface area is made available for charge storage and/or for increasing the coupling ratio of the memory cell. This allows the width of wing structures to be decreased, while maintaining a high coupling ratio. This greater surface area, by increasing the coupling ratio of the memory cell, also allows the use of low programming and erase voltages. Charge retention and coupling are also increased by substantially overlapping or encapsulating the floating gate by the control gate, thus keeping it isolated from other structures, such as sidewall spacers.

摘要翻译： 非易失性存储单元包括具有与形成在基板上的隧道层接触的底表面的浮动栅极，顶表面和沿着位线方向并沿着存储单元的字线方向定向的侧壁表面。 电介质层覆盖顶表面的至少一部分并且覆盖沿着位线和字线方向定向的表面的至少一部分。 控制栅极在其基本上所有的表面区域上与浮动栅极重叠。 提供了多个自对准侧壁间隔物，其设置成抵靠至少介电层和控制栅极侧壁。 通过在浮动栅极上重叠控制栅极，使更大的表面积可用于电荷存储和/或用于增加存储器单元的耦合比。 这允许翼结构的宽度减小，同时保持高耦合比。 通过增加存储单元的耦合比，该较大的表面积也允许使用低编程和擦除电压。 电荷保持和耦合也通过由控制栅极基本上重叠或封装浮置栅极而增加，从而使其与诸如侧壁间隔物的其它结构隔离。

公开(公告)号：US09425192B2

公开(公告)日：2016-08-23

申请号：US12332928

申请日：2008-12-11

申请人： Irfan Rahim ,  William Bradley Vest ,  Myron Wai Wong

发明人： Irfan Rahim ,  William Bradley Vest ,  Myron Wai Wong

IPC分类号： H01L29/00 ,  H01L27/08 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L27/0805 ,  H01L23/5223 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： Power supply decoupling capacitors are provided for integrated circuits. The decoupling capacitors may be distributed in clusters amongst powered circuit components. Each cluster may contain a number of individual capacitor cells that are connected in parallel. Each capacitor cell may contain a capacitor and a resistor connected in series with the capacitor. The capacitors may be metal-insulator-metal (MIM) capacitors. The resistor in each cell may limit the current through an individual capacitor in the event of a short in the capacitor due to a dielectric defect.

摘要翻译： 为集成电路提供电源去耦电容。 去耦电容器可以在电源电路组件之间分布成簇。 每个集群可以包含并联连接的多个单独的电容器单元。 每个电容器单元可以包含与电容器串联的电容器和电阻器。 电容器可以是金属 - 绝缘体 - 金属（MIM）电容器。 由于电介质缺陷，每个电池中的电阻可能会限制在电容器短路的情况下单个电容器的电流。

公开(公告)号：US08921170B1

公开(公告)日：2014-12-30

申请号：US13408959

申请日：2012-02-29

申请人： Jun Liu ,  Albert Ratnakumar ,  Mark T. Chan ,  Irfan Rahim

发明人： Jun Liu ,  Albert Ratnakumar ,  Mark T. Chan ,  Irfan Rahim

IPC分类号： H01L21/338

CPC分类号： H01L21/823418 ,  H01L21/324 ,  H01L21/823814 ,  H01L27/082 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66659

摘要： Asymmetric transistors such as asymmetric pass transistors may be formed on an integrated circuit. The asymmetric transistors may have gate structures. Symmetric pocket implants may be formed in source-drains on opposing sides of each transistor gate structure. Selective heating may be used to asymmetrically diffuse the implants. Selective heating may be implemented by patterning the gate structures on a semiconductor substrate so that the spacing between adjacent gate structures varies. A given gate structure may be located between first and second adjacent gate structures spaced at different respective distances from the given gate structure. A larger gate structure spacing leads to a greater substrate temperature rise than a smaller gate structure spacing. The pocket implant diffuses more in portions of the substrate with the greater temperature rise, producing asymmetric transistors. Asymmetric pass transistors may be controlled by static control signals from memory elements to implement circuits such as programmable multiplexers.

摘要翻译： 不对称晶体管，例如不对称传输晶体管可以形成在集成电路上。 不对称晶体管可以具有栅极结构。 可以在每个晶体管栅极结构的相对侧上的源极漏极中形成对称的袋状植入物。 选择性加热可用于不对称地扩散植入物。 可以通过在半导体衬底上图案化栅极结构来实现选择性加热，使得相邻栅极结构之间的间隔变化。 给定的栅极结构可以位于与给定栅极结构不同的相应距离处间隔开的第一和第二相邻栅极结构之间。 较大的栅极结构间隔导致比较小栅极结构间隔更大的衬底温度升高。 在较大的温度上升的情况下，口袋植入物在衬底的部分扩散，产生不对称晶体管。 不对称传输晶体管可以由来自存储器元件的静态控制信号来控制，以实现诸如可编程多路复用器之类的电路。

公开(公告)号：US08804407B1

公开(公告)日：2014-08-12

申请号：US13181219

申请日：2011-07-12

申请人： Jun Liu ,  Albert Ratnakumar ,  Irfan Rahim ,  Qi Xiang

发明人： Jun Liu ,  Albert Ratnakumar ,  Irfan Rahim ,  Qi Xiang

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  H03K2217/0054

摘要： An IC that includes a memory cell and a pass gate coupled to the memory cell, where the pass gate includes a PMOS transistor, is described. In one implementation, the PMOS transistor has a negative threshold voltage. In one implementation, the memory cell includes thick oxide transistors.

摘要翻译： 描述了包括耦合到存储器单元的存储单元和通过栅极的IC，其中栅极包括PMOS晶体管。 在一个实现中，PMOS晶体管具有负阈值电压。 在一个实现中，存储单元包括厚的氧化物晶体管。