公开(公告)号：US09659954B2

公开(公告)日：2017-05-23

申请号：US14702038

申请日：2015-05-01

Applicant: Hyun-suk Kim ,  Joon-hee Lee ,  Kee-jeong Rho

Inventor： Hyun-suk Kim ,  Joon-hee Lee ,  Kee-jeong Rho

IPC: H01L29/94 ,  H01L29/76 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L49/02 ,  H01L27/1157 ,  H01L27/11573

CPC classification number: H01L27/11573 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11582 ,  H01L28/60 ,  H01L28/91

Abstract: Provided is a vertical non-volatile memory device in which a capacitor constituting a peripheral circuit region is formed as a vertical type so that an area occupied by the capacitor in the entire device can be reduced as compared with a planar capacitor. Thus, a non-volatile memory device may be highly integrated and have a high capacity. The device includes a substrate having a cell region and a peripheral circuit region, a memory cell string including a plurality of vertical memory cells formed in the cell region and channel holes formed to penetrate the vertical memory cells in a first direction vertical to the substrate, an insulating layer formed in the peripheral circuit region on the substrates at substantially the same level as an upper surface of the memory cell string, and a plurality of capacitor electrodes formed on the peripheral circuit region to penetrate at least a portion of the insulating layer in the first direction, the plurality of capacitor electrodes extending parallel to the channel holes. The plurality of capacitor electrodes are spaced apart from one another in a second direction parallel to the substrate, and the insulating layer is interposed between a pair of adjacent capacitor electrodes from among the plurality of capacitor electrodes.

公开(公告)号：US09484354B2

公开(公告)日：2016-11-01

申请号：US14637538

申请日：2015-03-04

Applicant: Sung-Hun Lee ,  Jong-Ho Park ,  Joon-Hee Lee ,  Hee-Jueng Lee

Inventor： Sung-Hun Lee ,  Jong-Ho Park ,  Joon-Hee Lee ,  Hee-Jueng Lee

IPC: H01L29/792 ,  H01L27/115 ,  H01L29/04

CPC classification number: H01L27/11573 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/045

Abstract: A memory device includes a memory cell on a first region of a substrate. An active region is in a second region neighboring the first region of the substrate, and an extension direction of the active region has an acute angle with the direction of the substrate. A transistor serving as a peripheral circuit is on the second region of the substrate. In the memory device, defects or failures due to a crystal defects or a dislocation of the substrate may decrease.

Abstract translation: 存储器件包括在衬底的第一区域上的存储器单元。 有源区域位于与衬底的第一区域相邻的第二区域中，并且有源区域的延伸方向与衬底的<110>方向成锐角。 用作外围电路的晶体管位于衬底的第二区域上。 在存储器件中，由于晶体缺陷或衬底的位错导致的缺陷或故障可能降低。

公开(公告)号：US09281414B2

公开(公告)日：2016-03-08

申请号：US14151288

申请日：2014-01-09

Applicant: Jin-Yeon Won ,  Joon-Hee Lee ,  Seung-Woo Paek ,  Dong-Seog Eun

Inventor： Jin-Yeon Won ,  Joon-Hee Lee ,  Seung-Woo Paek ,  Dong-Seog Eun

IPC: H01L29/792 ,  H01L27/115 ,  H01L29/66

CPC classification number: H01L29/42344 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

Abstract: According to example embodiments of inventive concepts, a semiconductor device includes: a substrate, and a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate. The stacked structure defines a through-hole over the substrate. The gate electrodes each include a first portion between the through-hole and a second portion of the gate electrodes. A channel pattern may be in the through-hole. A tunneling layer may surround the channel pattern. A charge trap layer may surround the tunneling layer, and protective patterns may surround the first portions of the gate electrodes. The protective patterns may be between the first portions of the gate electrodes and the charge trap layer.

Abstract translation: 根据本发明构思的示例性实施例，半导体器件包括：衬底，以及包括层间绝缘层和交替层叠在衬底上的栅电极的堆叠结构。 堆叠结构在衬底上限定通孔。 栅电极各自包括在通孔和栅电极的第二部分之间的第一部分。 通道图案可以在通孔中。 隧道层可围绕通道图案。 电荷陷阱层可围绕隧道层，并且保护图案可围绕栅电极的第一部分。 保护图案可以在栅电极的第一部分和电荷陷阱层之间。

公开(公告)号：US20150348987A1

公开(公告)日：2015-12-03

申请号：US14637538

申请日：2015-03-04

Applicant: SUNG-HUN LEE ,  JONG-HO PARK ,  JOON-HEE LEE ,  HEE-JUENG LEE

Inventor： SUNG-HUN LEE ,  JONG-HO PARK ,  JOON-HEE LEE ,  HEE-JUENG LEE

IPC: H01L27/115 ,  H01L29/04

CPC classification number: H01L27/11573 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/045

Abstract: A memory device includes a memory cell on a first region of a substrate. An active region is in a second region neighboring the first region of the substrate, and an extension direction of the active region has an acute angle with the direction of the substrate. A transistor serving as a peripheral circuit is on the second region of the substrate. In the memory device, defects or failures due to a crystal defects or a dislocation of the substrate may decrease.

Abstract translation: 存储器件包括在衬底的第一区域上的存储器单元。 有源区域位于与衬底的第一区域相邻的第二区域中，并且有源区域的延伸方向与衬底的<110>方向成锐角。 用作外围电路的晶体管位于衬底的第二区域上。 在存储器件中，由于晶体缺陷或衬底的位错导致的缺陷或故障可能降低。

公开(公告)号：US09059015B2

公开(公告)日：2015-06-16

申请号：US13237778

申请日：2011-09-20

Applicant: Won Cheol Seo ,  Joon Hee Lee ,  Jong Kyun You ,  Chang Youn Kim ,  Jin Cheul Shin ,  Hwa Mok Kim ,  Jang Woo Lee ,  Yeo Jin Yoon ,  Jong Kyu Kim

Inventor： Won Cheol Seo ,  Joon Hee Lee ,  Jong Kyun You ,  Chang Youn Kim ,  Jin Cheul Shin ,  Hwa Mok Kim ,  Jang Woo Lee ,  Yeo Jin Yoon ,  Jong Kyu Kim

IPC: H01L25/075 ,  H01L27/15 ,  H01L33/62 ,  H01L33/00 ,  H01L33/46

CPC classification number: H01L33/60 ,  H01L25/0753 ,  H01L27/156 ,  H01L33/007 ,  H01L33/0079 ,  H01L33/06 ,  H01L33/22 ,  H01L33/32 ,  H01L33/46 ,  H01L33/62 ,  H01L2924/0002 ,  H01L2933/0058 ,  H01L2933/0066 ,  H01L2924/00

Abstract: Disclosed are a light emitting device and a method of fabricating the same. The light emitting device comprises a substrate. A plurality of light emitting cells are disposed on top of the substrate to be spaced apart from one another. Each of the light emitting cells comprises a first upper semiconductor layer, an active layer, and a second lower semiconductor layer. Reflective metal layers are positioned between the substrate and the light emitting cells. The reflective metal layers are prevented from being exposed to the outside.

Abstract translation: 公开了一种发光器件及其制造方法。 发光器件包括衬底。 多个发光单元设置在基板的顶部上以彼此间隔开。 每个发光单元包括第一上半导体层，有源层和第二下半导体层。 反射金属层位于基板和发光单元之间。 防止反射金属层暴露于外部。

公开(公告)号：US09029888B2

公开(公告)日：2015-05-12

申请号：US13109669

申请日：2011-05-17

Applicant: Chang Yeon Kim ,  Da Hye Kim ,  Hong Chul Lim ,  Joon Hee Lee ,  Jong Kyun You

Inventor： Chang Yeon Kim ,  Da Hye Kim ,  Hong Chul Lim ,  Joon Hee Lee ,  Jong Kyun You

IPC: H01L33/00 ,  H01L33/38 ,  H01L33/46 ,  H01L33/22

CPC classification number: H01L33/382 ,  H01L33/007 ,  H01L33/0079 ,  H01L33/20 ,  H01L33/22 ,  H01L33/32 ,  H01L33/38 ,  H01L33/40 ,  H01L33/405 ,  H01L33/46 ,  H01L2224/48463 ,  H01L2224/73265

Abstract: Exemplary embodiments of the present invention relate to a high-efficiency light emitting diode (LED). The LED according to an exemplary embodiment includes a substrate, a semiconductor stack arranged on the substrate, wherein the semiconductor stack has a p-type semiconductor layer, an active layer and an n-type semiconductor layer, a first metal layer interposed between the substrate and the semiconductor stack, the first metal layer ohmic-contacted with the semiconductor stack, a first electrode pad arranged on the semiconductor stack, an electrode extension extending from the first electrode pad, wherein the electrode extension has a contact region contacting the n-type semiconductor layer, a first insulating layer interposed between the substrate and the semiconductor stack, wherein the first insulating layer covers a surface region of the p-type semiconductor layer under the contact region of the electrode extension, and a second insulating layer interposed between the first electrode pad and the semiconductor stack.

Abstract translation: 本发明的示例性实施例涉及一种高效率发光二极管（LED）。 根据示例性实施例的LED包括衬底，布置在衬底上的半导体堆叠，其中半导体堆叠具有p型半导体层，有源层和n型半导体层，插入在衬底之间的第一金属层 半导体堆叠，与半导体堆叠欧姆接触的第一金属层，布置在半导体堆叠上的第一电极焊盘，从第一电极焊盘延伸的电极延伸部，其中电极延伸部具有接触n型 半导体层，插入在所述基板和所述半导体堆叠之间的第一绝缘层，其中所述第一绝缘层覆盖所述电极延伸部的接触区域下方的所述p型半导体层的表面区域，以及插入在所述第一绝缘层之间的第二绝缘层 电极焊盘和半导体堆叠。

公开(公告)号：US08772805B2

公开(公告)日：2014-07-08

申请号：US13018557

申请日：2011-02-01

Applicant: Kyung Hee Ye ,  Chang Youn Kim ,  Jin Cheol Shin ,  Joon Hee Lee ,  Jong Kyun You ,  Hong Chol Lim

Inventor： Kyung Hee Ye ,  Chang Youn Kim ,  Jin Cheol Shin ,  Joon Hee Lee ,  Jong Kyun You ,  Hong Chol Lim

IPC: H01L33/00

CPC classification number: H01L33/46 ,  H01L33/0079 ,  H01L33/20 ,  H01L33/22 ,  H01L33/24 ,  H01L33/387 ,  H01L33/42 ,  H01L33/44

Abstract: A high-efficiency light emitting diode including: a semiconductor stack positioned on a support substrate, including a p-type compound semiconductor layer, an active layer, and an n-type compound semiconductor layer; an insulating layer disposed in an opening that divides the p-type compound semiconductor layer and active layer; a transparent electrode layer disposed on the insulating layer and the p-type compound semiconductor layer; a reflective insulating layer covering the transparent electrode layer, to reflect light from the active layer away from the support substrate; a p-electrode covering the reflective insulating layer; and an n-electrode is formed on top of the n-type compound semiconductor layer. The p-electrode is electrically connected to the transparent electrode layer through the insulating layer.

公开(公告)号：US08648369B2

公开(公告)日：2014-02-11

申请号：US13073794

申请日：2011-03-28

Applicant: Won Cheol Seo ,  Joon Hee Lee ,  Jong Kyun You ,  Chang Youn Kim ,  Jin Cheul Shin ,  Hwa Mok Kim ,  Jang Woo Lee ,  Yeo Jin Yoon ,  Jong Kyu Kim

Inventor： Won Cheol Seo ,  Joon Hee Lee ,  Jong Kyun You ,  Chang Youn Kim ,  Jin Cheul Shin ,  Hwa Mok Kim ,  Jang Woo Lee ,  Yeo Jin Yoon ,  Jong Kyu Kim

IPC: H01L33/60

CPC classification number: H01L33/60 ,  H01L25/0753 ,  H01L27/156 ,  H01L33/007 ,  H01L33/0079 ,  H01L33/06 ,  H01L33/22 ,  H01L33/32 ,  H01L33/46 ,  H01L33/62 ,  H01L2924/0002 ,  H01L2933/0058 ,  H01L2933/0066 ,  H01L2924/00

Abstract: Disclosed are a light emitting device and a method of fabricating the same. The light emitting device comprises a substrate. A plurality of light emitting cells are disposed on top of the substrate to be spaced apart from one another. Each of the light emitting cells comprises a first upper semiconductor layer, an active layer, and a second lower semiconductor layer. Reflective metal layers are positioned between the substrate and the light emitting cells. The reflective metal layers are prevented from being exposed to the outside.

Abstract translation: 公开了一种发光器件及其制造方法。 发光器件包括衬底。 多个发光单元设置在基板的顶部上以彼此间隔开。 每个发光单元包括第一上半导体层，有源层和第二下半导体层。 反射金属层位于基板和发光单元之间。 防止反射金属层暴露于外部。

公开(公告)号：US08555058B2

公开(公告)日：2013-10-08

申请号：US11585109

申请日：2006-10-24

Applicant: Jun-hae Choi ,  In-hwan Kim ,  Seung-gi Chang ,  Joon-hee Lee ,  Ju-han Lee ,  Ji-hoon Kim ,  Ho-jeong You

Inventor： Jun-hae Choi ,  In-hwan Kim ,  Seung-gi Chang ,  Joon-hee Lee ,  Ju-han Lee ,  Ji-hoon Kim ,  Ho-jeong You

IPC: H04L29/06

CPC classification number: H04B3/54 ,  H04B2203/5445

Abstract: A method of distributing group identifiers IDs (GIDs) in a power line communication (PLC) network, a method of receiving the GIDs, an authentication apparatus, and a PLC apparatus are provided. The authentication apparatus includes: an authentication mode storing unit which stores an authentication mode having a value including one of an authentication authorized mode and an authentication unauthorized mode; a GID request receiver which receives a GID request message from a PLC apparatus; and a GID transmitter which, if the authentication mode is the authentication authorized mode, transmits a GID corresponding to the PLC apparatus to the PLC apparatus. Authentication is realized in a PLC media access control layer distributing the GIDs between a PLC apparatus and an authentication apparatus, so manually inputting a GID into the PLC apparatus is not necessary. Further, the GIDs are distributed via the authentication apparatus, thereby centrally managing the GIDs.

Abstract translation: 提供了在电力线通信（PLC）网络中分发组标识符ID（GID）的方法，接收GID的方法，认证装置和PLC装置。 认证装置包括：认证模式存储单元，其存储具有认证授权模式和认证未授权模式之一的值的认证模式; GID请求接收器，其从PLC装置接收GID请求消息; 以及GID发送器，如果认证方式是认证授权模式，则向PLC装置发送与PLC装置对应的GID。 在PLC装置和认证装置之间的分配GID的PLC媒体访问控制层中实现认证，因此不需要手动地将GID输入到PLC装置。 此外，GID通过认证装置分发，从而集中管理GID。

公开(公告)号：US08320243B2

公开(公告)日：2012-11-27

申请号：US11599262

申请日：2006-11-15

Applicant: Jun-hae Choi ,  In-hwan Kim ,  Seung-gi Chang ,  Joon-hee Lee ,  Ju-han Lee ,  Ho-jeong You

Inventor： Jun-hae Choi ,  In-hwan Kim ,  Seung-gi Chang ,  Joon-hee Lee ,  Ju-han Lee ,  Ho-jeong You

IPC: G01R31/08 ,  H04L12/28

CPC classification number: H04L47/10 ,  H04B2203/5445 ,  H04L47/2416 ,  H04L47/2433 ,  H04L47/2458

Abstract: A method of transmitting data more effectively, and more particularly, a method of classifying service traffic, transmitting data according to the classifications of the service traffic, and performing a contention free slot (CFS) allocation in order to transmit data in a power line communication (PLC) network, and an apparatus to do the same. The data transmission method includes determining transmission priority of data according to service traffic characteristics, and transmitting data according to the determined transmission priority, thereby providing differentiated quality of service (QoS) according to service traffic characteristics.

Abstract translation: 一种更有效地发送数据的方法，更具体地，涉及一种分类业务流量，根据业务流量分类发送数据，执行无竞争时隙（CFS）分配的方法，以便在电力线通信中发送数据 （PLC）网络，以及进行相同操作的设备。 数据传输方法包括根据业务流量特性确定数据的传输优先级，并根据确定的传输优先级发送数据，从而根据业务流量特性提供差异化​​的服务质量（QoS）。