公开(公告)号：US06258700B1

公开(公告)日：2001-07-10

申请号：US09313830

申请日：1999-05-18

Applicant: Mark T. Bohr ,  Mohsen Alavi

Inventor： Mark T. Bohr ,  Mohsen Alavi

IPC: H01L21326

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fusible link device disposed on a semiconductor substrate for providing discretionary electrical connections. The fusible link device of the invention includes a silicide layer and a polysilicon layer formed on the silicide layer and has a first un-programmed resistance. The silicide layer agglomerates to form an electrical discontinuity in response to a predetermined programming potential being applied across the suicide layer, such that the resistance of the fusible link device can be selectively increased to a second programmed resistance.

Abstract translation: 一种设置在半导体衬底上用于提供任意电连接的可熔连接装置。 本发明的可熔连接装置包括硅化物层和形成在硅化物层上并具有第一非编程电阻的多晶硅层。 硅化物层聚集形成响应于在硅化物层上施加的预定编程电位的电中断，使得可熔接线器件的电阻可以选择性地增加到第二编程电阻。

公开(公告)号：US5420051A

公开(公告)日：1995-05-30

申请号：US174291

申请日：1993-12-28

Applicant: Mark T. Bohr ,  Richard G. Taylor ,  Stephen T. Chambers

Inventor： Mark T. Bohr ,  Richard G. Taylor ,  Stephen T. Chambers

IPC: H01L21/331 ,  H01L21/265 ,  H01L21/44

CPC classification number: H01L29/66272 ,  Y10S148/01

Abstract: A process of forming an emitter of a bipolar transistor is described. Dopants of a first conductivity type is implanted in the substrate to form the base. Dopants of a second conductivity type is then implanted into the base region to form a substrate emitter region. A polysilicon layer is then deposited over the substrate emitter and doped to form the doped polysilicon layer. An outdiffusion step follows to link the doped polysilicon layer to the substrate emitter.

Abstract translation: 描述形成双极晶体管的发射极的工艺。 将第一导电类型的掺杂剂注入到基板中以形成基底。 然后将第二导电类型的掺杂剂注入到基极区域中以形成衬底发射极区域。 然后将多晶硅层沉积在衬底发射极上并掺杂以形成掺杂多晶硅层。 将掺杂多晶硅层连接到衬底发射极之后，进行扩散步骤。

公开(公告)号：US4364075A

公开(公告)日：1982-12-14

申请号：US182870

申请日：1980-09-02

Applicant: Mark T. Bohr ,  Kenneth K. Yu ,  Ronald J. C. Chwang ,  Neil C. Berglund

Inventor： Mark T. Bohr ,  Kenneth K. Yu ,  Ronald J. C. Chwang ,  Neil C. Berglund

IPC: G11C11/401 ,  G11C5/00 ,  G11C11/404 ,  H01L21/822 ,  H01L21/8242 ,  H01L23/556 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L27/02

CPC classification number: H01L27/10805 ,  G11C11/404 ,  G11C5/005 ,  H01L23/556 ,  H01L2924/0002

Abstract: A high density CMOS dynamic RAM cell comprising a transistor and capacitance means formed in an n-well is disclosed. The capacitance means includes a polysilicon plate member disposed above a p-type region formed in the n-well. A buried contact, extending from the plate member, pierces the p-type region and contacts the well. In addition to the capacitance associated with the plate member, p-type region and well, capacitance is obtained between the side walls of the n-type regions and p-type regions.

Abstract translation: 公开了一种包括形成在n阱中的晶体管和电容装置的高密度CMOS动态RAM单元。 电容装置包括设置在形成在n阱中的p型区域上方的多晶硅板构件。 从板构件延伸的埋入触头刺穿p型区域并与阱接触。 除了与板构件，p型区域和阱相关联的电容之外，在n型区域和p型区域的侧壁之间获得电容。

公开(公告)号：US09093513B2

公开(公告)日：2015-07-28

申请号：US13786372

申请日：2013-03-05

Applicant: Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

Inventor： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC: H01L29/66 ,  H01L29/417 ,  H01L21/336 ,  H01L21/28 ,  H01L21/463 ,  H01L29/78 ,  H01L21/768 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L21/76897 ,  H01L21/28123 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/28562 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US20140191419A1

公开(公告)日：2014-07-10

申请号：US13995917

申请日：2011-12-22

Applicant: Debendra Mallik ,  Ram S. Viswanath ,  Sriram Srinivasan ,  Mark T. Bohr ,  Andrew W. Yeoh ,  Sairam Agraharam

Inventor： Debendra Mallik ,  Ram S. Viswanath ,  Sriram Srinivasan ,  Mark T. Bohr ,  Andrew W. Yeoh ,  Sairam Agraharam

IPC: H01L25/065 ,  H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/00

Abstract: 3D integrated circuit packages with window interposers and methods to form such semiconductor packages are described. For example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer having a window is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in the window of the interposer and interconnected to the top semiconductor die. In another example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in a same plane as the interposer and interconnected to the top semiconductor die.

Abstract translation: 描述了具有窗口插入件的3D集成电路封装和形成这种半导体封装的方法。 例如，半导体封装包括衬底。 顶部半导体管芯设置在衬底上方。 具有窗口的插入件设置在基板和顶部半导体管芯之间并与之互连。 底部半导体管芯设置在插入件的窗口中并且互连到顶部半导体管芯。 在另一示例中，半导体封装包括衬底。 顶部半导体管芯设置在衬底上方。 插入器设置在衬底和顶部半导体管芯之间并且互连到衬底和顶部半导体管芯。 底部半导体管芯设置在与插入器相同的平面中并且互连到顶部半导体管芯。

公开(公告)号：US20130178033A1

公开(公告)日：2013-07-11

申请号：US13786372

申请日：2013-03-05

Applicant: Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

Inventor： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC: H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/28123 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/28562 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US20080135894A1

公开(公告)日：2008-06-12

申请号：US12009122

申请日：2008-01-15

Applicant: Mark T. Bohr ,  Steven J. Keating ,  Thomas A. Letson ,  Anand S. Murthy ,  Donald W. O'Neill ,  Willy Rachmady

Inventor： Mark T. Bohr ,  Steven J. Keating ,  Thomas A. Letson ,  Anand S. Murthy ,  Donald W. O'Neill ,  Willy Rachmady

IPC: H01L29/94

CPC classification number: H01L29/045 ,  H01L21/30608 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.

Abstract translation: 实施例是改进的晶体管结构和制造该结构的方法。 特别地，实施例的湿蚀刻形成具有改进的尖端形状的源极和漏极区域，以通过改善短沟道效应的控制，增加饱和电流，改善冶金栅极长度的控制，增加载流子迁移率来提高晶体管的性能 并且在源极和漏极与硅化物之间的界面处降低接触电阻。

公开(公告)号：US06982225B2

公开(公告)日：2006-01-03

申请号：US10660421

申请日：2003-09-10

Applicant: Mark T. Bohr

Inventor： Mark T. Bohr

IPC: H01L21/31

CPC classification number: H01L23/147 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/157 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49165

Abstract: A structure suitable for connecting an integrated circuit to a supporting substrate wherein the structure has thermal expansion characteristics well-matched to the integrated circuit is an interposer. The integrated circuit and the interposer are comprised of bodies that have substantially similar coefficients of thermal expansion. The interposer has a first surface adapted to electrically and mechanically couple to the integrated circuit. The interposer has a second surface adapted to electrically and mechanically couple to a supporting substrate. Electrically conductive vias provide signal pathways between the first surface and the second surface of the interposer. Various circuit elements may be incorporated into the interposer. These circuit elements may be active, passive, or a combination of active and passive elements.

公开(公告)号：US6020244A

公开(公告)日：2000-02-01

申请号：US777552

申请日：1996-12-30

Applicant: Scott E. Thompson ,  Paul A. Packan ,  Tahir Ghani ,  Mark Stettler ,  Shahriar S. Ahmed ,  Mark T. Bohr

Inventor： Scott E. Thompson ,  Paul A. Packan ,  Tahir Ghani ,  Mark Stettler ,  Shahriar S. Ahmed ,  Mark T. Bohr

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/10

CPC classification number: H01L29/66492 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/6659

Abstract: An improved well boosting implant which provides better characteristics than traditional halo implants particularly for short channel devices (e.g., 0.25 microns or less). In effect, an implant is distributed across the entire channel with higher concentrations occurring in the center of the channel of the devices having gate lengths less than the critical dimension. This is done by using very large tilt angles (e.g., 30-50.degree.) with a relatively light dopant species and by using a relatively high energy when compared to the traditional halo implants.

Abstract translation: 一种改进的促进良好的植入物，其具有比传统的晕轮植入物更好的特征，特别是对于短通道装置（例如，0.25微米或更小）。 实际上，植入物分布在整个通道上，较高的浓度出现在栅极长度小于临界尺寸的器件的通道的中心。 这通过使用具有相对较轻的掺杂物质的非常大的倾斜角（例如，30-50°）和与传统的晕轮植入物相比使用相当高的能量来完成。

公开(公告)号：US5969404A

公开(公告)日：1999-10-19

申请号：US895325

申请日：1997-07-16

Applicant: Mark T. Bohr ,  Mohsen Alavi

Inventor： Mark T. Bohr ,  Mohsen Alavi

IPC: H01L21/82 ,  H01L23/525 ,  H01L29/00

CPC classification number: H01L23/5256 ,  H01L2924/0002

Abstract: A fusible link device disposed on a semiconductor substrate for providing discretionary electrical connections. The fusible link device of the invention includes a silicide layer and a polysilicon layer formed on the silicide layer and has a first unprogrammed resistance. The silicide layer agglomerates to form an electrical discontinuity in response to a predetermined programming potential being applied across the silicide layer, such that the resistance of the fusible link device can be selectively increased to a second programmed resistance

Abstract translation: 一种设置在半导体衬底上用于提供任意电连接的可熔连接装置。 本发明的熔断连接装置包括在硅化物层上形成的硅化物层和多晶硅层，并具有第一未编程电阻。 硅化物层聚集形成响应于跨越硅化物层施加的预定编程电位的电中断，使得可熔接头装置的电阻可以选择性地增加到第二编程电阻