公开(公告)号：US20240321833A1

公开(公告)日：2024-09-26

申请号：US18733580

申请日：2024-06-04

Applicant: Apple Inc.

Inventor： Jun Zhai

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L2224/05009 ,  H01L2225/06513

Abstract: Reconstructed 3DIC structures and methods of manufacture are described. In an embodiment, one or more dies in each package level of a 3DIC are both functional chips and/or stitching devices for two or more dies in an adjacent package level. Thus, each die can function as a communication bridge between two other dies/chiplets in addition to performing a separate chip core function.

公开(公告)号：US12087689B2

公开(公告)日：2024-09-10

申请号：US18488561

申请日：2023-10-17

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Jung-Cheng Yeh ,  Kunzhong Hu ,  Raymundo Camenforte ,  Thomas Hoffmann

IPC: H01L21/00 ,  H01L23/48 ,  H01L23/528 ,  H01L23/538 ,  H01L23/58 ,  H01L25/065 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L23/528 ,  H01L23/481 ,  H01L23/5386 ,  H01L23/585 ,  H01L25/0652 ,  H01L25/0655 ,  H01L21/78 ,  H01L22/20 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/30 ,  H01L24/32 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/30181 ,  H01L2224/32145 ,  H01L2224/32225

Abstract: Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.

公开(公告)号：US12074077B2

公开(公告)日：2024-08-27

申请号：US16952567

申请日：2020-11-19

Applicant: Apple Inc.

Inventor： Karthik Shanmugam ,  Flynn P. Carson ,  Jun Zhai ,  Raymundo M. Camenforte ,  Menglu Li

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/02 ,  H01L23/48

CPC classification number: H01L23/3121 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/31 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/4985 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/24 ,  H01L25/0655 ,  H01L25/105 ,  H05K1/0278 ,  H01L23/481 ,  H01L23/5384 ,  H01L2224/24137 ,  H01L2225/06548 ,  H01L2924/18162

Abstract: Flexible packages and electronic devices with integrated flexible packages are described. In an embodiment, a flexibly package includes a first die and a second die encapsulated in a molding compound layer. A compliant redistribution layer (RDL) spans the molding compound layer and both dies, and includes electrical routing formed directly on landing pads of the dies. A notch is formed in the molding compound layer between the dies to facilitate flexure of the compliant RDL.

公开(公告)号：US20240243012A1

公开(公告)日：2024-07-18

申请号：US18622588

申请日：2024-03-29

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu ,  Shawn Searles ,  Joseph T. DiBene, II ,  Mengzhi Pang

IPC: H01L21/77 ,  H01L21/66 ,  H01L23/00 ,  H01L25/03 ,  H01L25/16 ,  H01L25/18

CPC classification number: H01L21/77 ,  H01L22/20 ,  H01L24/32 ,  H01L24/73 ,  H01L25/03 ,  H01L25/16 ,  H01L25/18 ,  H01L24/17 ,  H01L2224/12105 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/24195 ,  H01L2924/12 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104

Abstract: Systems including voltage regulator circuits are disclosed. In one embodiment, an apparatus includes a voltage regulator controller integrated circuit (IC) die including one or more portions of a voltage regulator circuit. The apparatus further includes a capacitor die, an inductor die, and an interconnect layer arranged over the voltage regulator controller IC die, the capacitor die and the inductor die. The interconnect provides electrical connections between the voltage regulator controller IC die, the capacitor die and the inductor die to form the voltage regulator circuit. In a further embodiment, the voltage regulator controller IC die, the capacitor die and the inductor die are arranged in a planar fashion within a voltage regulator module. In still another embodiment, a system IC is coupled to the voltage regulator module and includes one or more functional circuit blocks coupled to receive a regulated supply voltage generated by the voltage regulator circuit.

公开(公告)号：US20230402373A1

公开(公告)日：2023-12-14

申请号：US18339132

申请日：2023-06-21

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Kunzhong Hu ,  Raymundo M. Camenforte

IPC: H01L23/528 ,  H01L23/58 ,  H01L25/18 ,  H01L23/00

CPC classification number: H01L23/528 ,  H01L23/585 ,  H01L25/18 ,  H01L24/16 ,  H01L24/32 ,  H01L24/08 ,  H01L2224/32145 ,  H01L2224/16145 ,  H01L2224/16265 ,  H01L2224/08145

Abstract: Multi-die structures with die-to-die routing are described. In an embodiment, each die is patterned into the same semiconductor substrate, and the dies may be interconnected with die-to-die routing during back-end wafer processing. Partial metallic seals may be formed to accommodate the die-to-die routing, programmable dicing, and various combinations of full metallic seals and partial metallic seals can be formed. This may also be extended to three dimensional structures formed using wafer-on-wafer or chip-on-wafer techniques.

公开(公告)号：US20230335440A1

公开(公告)日：2023-10-19

申请号：US18307554

申请日：2023-04-26

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu ,  Shawn Searles ,  Joseph T. DiBene, II ,  Mengzhi Pang

IPC: H01L21/77 ,  H01L25/16 ,  H01L25/03 ,  H01L25/18 ,  H01L21/66 ,  H01L23/00

CPC classification number: H01L21/77 ,  H01L25/16 ,  H01L25/03 ,  H01L25/18 ,  H01L22/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/17 ,  H01L2924/1427 ,  H01L2924/1436 ,  H01L2924/19042 ,  H01L2924/1432 ,  H01L2924/19103 ,  H01L2224/12105 ,  H01L2224/1703 ,  H01L2924/19104 ,  H01L2224/16265 ,  H01L2924/15192 ,  H01L2224/16235 ,  H01L2924/19041 ,  H01L2224/16227 ,  H01L2224/24195 ,  H01L2924/1433 ,  H01L2924/18162 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2224/17181 ,  H01L2924/12 ,  H01L2924/1205 ,  H01L2924/1206

Abstract: Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.

公开(公告)号：US20230317708A1

公开(公告)日：2023-10-05

申请号：US18194236

申请日：2023-03-31

Applicant: Apple Inc.

Inventor： Wei Chen ,  Jie-Hua Zhao ,  Jun Zhai ,  Po-Hao Chang ,  Hsien-Che Lin ,  Ying-Chieh Ke ,  Kunzhong Hu

IPC: H01L25/18 ,  H01L23/24

CPC classification number: H01L25/18 ,  H01L23/24

Abstract: Multiple chip module (MCM) structures are described. In an embodiment, a module includes a first and second components on the top side of a module substrate, a stiffener structure mounted on the top side of the module substrate, and a lid mounted on the stiffener structure and covering the first component and the second component. The stiffener is joined to the lid within a trench formed in a roof of the lid.

公开(公告)号：US20230223348A1

公开(公告)日：2023-07-13

申请号：US18163033

申请日：2023-02-01

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu

IPC: H01L23/538 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065 ,  H01L21/683 ,  H01L25/10 ,  H01L23/16 ,  H01L23/498 ,  H01L23/31 ,  H01L25/18

CPC classification number: H01L23/5385 ,  H01L25/50 ,  H01L21/486 ,  H01L24/96 ,  H01L25/0655 ,  H01L23/5383 ,  H01L24/19 ,  H01L23/5386 ,  H01L21/4853 ,  H01L21/6835 ,  H01L25/105 ,  H01L23/16 ,  H01L23/5384 ,  H01L23/49833 ,  H01L2924/15192 ,  H01L2224/92125 ,  H01L24/16 ,  H01L23/49827 ,  H01L2225/1023 ,  H01L2924/19105 ,  H01L2924/19011 ,  H01L2224/131 ,  H01L2224/12105 ,  H01L23/3128 ,  H01L2924/37001 ,  H01L2224/81005 ,  H01L2225/1094 ,  H01L2924/3511 ,  H01L2224/92225 ,  H01L2224/16237 ,  H01L23/49822 ,  H01L2924/1432 ,  H01L2224/04105 ,  H01L2924/15311 ,  H01L2924/1431 ,  H01L2224/16227 ,  H01L2221/68359 ,  H01L2924/19043 ,  H01L24/73 ,  H01L23/49816 ,  H01L2224/1703 ,  H01L2924/1434 ,  H01L24/17 ,  H01L21/4857 ,  H01L2224/16235 ,  H01L2224/0401 ,  H01L2924/19042 ,  H01L2924/19041 ,  H01L2224/73267 ,  H01L2225/1058 ,  H01L2224/73253 ,  H01L24/13 ,  H01L25/18 ,  H01L2224/97 ,  H01L2224/92244 ,  H01L2224/32225 ,  H01L24/32 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/73204

Abstract: Multiple component package structures are described in which an interposer chiplet is integrated to provide fine routing between components. In an embodiment, the interposer chiplet and a plurality of conductive vias are encapsulated in an encapsulation layer. A first plurality of terminals of the first and second components may be in electrical connection with the plurality of conductive pillars and a second plurality of terminals of first and second components may be in electrical connection with the interposer chiplet.

公开(公告)号：US11670548B2

公开(公告)日：2023-06-06

申请号：US17080609

申请日：2020-10-26

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu ,  Shawn Searles ,  Joseph T. DiBene, II ,  Mengzhi Pang

IPC: H01L21/77 ,  H01L25/16 ,  H01L25/03 ,  H01L25/18 ,  H01L21/66 ,  H01L23/00

CPC classification number: H01L21/77 ,  H01L22/20 ,  H01L24/32 ,  H01L24/73 ,  H01L25/03 ,  H01L25/16 ,  H01L25/18 ,  H01L24/17 ,  H01L2224/12105 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/24195 ,  H01L2924/12 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104

Abstract: Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.

公开(公告)号：US20230085890A1

公开(公告)日：2023-03-23

申请号：US17483535

申请日：2021-09-23

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Jung-Cheng Yeh ,  Kunzhong Hu ,  Raymundo Camenforte ,  Thomas Hoffmann

IPC: H01L23/528 ,  H01L23/58 ,  H01L23/538 ,  H01L23/48 ,  H01L25/065

Abstract: Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.